d1_pac/usb1/hci_controller_phy_interface/
hci_interface.rs

1#[doc = "Register `hci_interface` reader"]
2pub type R = crate::R<HCI_INTERFACE_SPEC>;
3#[doc = "Register `hci_interface` writer"]
4pub type W = crate::W<HCI_INTERFACE_SPEC>;
5#[doc = "Field `ulpi_bypass_enable` reader - ULPI bypass enable"]
6pub type ULPI_BYPASS_ENABLE_R = crate::BitReader<ULPI_BYPASS_ENABLE_A>;
7#[doc = "ULPI bypass enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum ULPI_BYPASS_ENABLE_A {
10    #[doc = "1: Enable UTMI interface, disable ULPI interface"]
11    UTMI = 1,
12    #[doc = "0: Enable ULPI interface, disable UTMI interface"]
13    ULPI = 0,
14}
15impl From<ULPI_BYPASS_ENABLE_A> for bool {
16    #[inline(always)]
17    fn from(variant: ULPI_BYPASS_ENABLE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl ULPI_BYPASS_ENABLE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> ULPI_BYPASS_ENABLE_A {
25        match self.bits {
26            true => ULPI_BYPASS_ENABLE_A::UTMI,
27            false => ULPI_BYPASS_ENABLE_A::ULPI,
28        }
29    }
30    #[doc = "Enable UTMI interface, disable ULPI interface"]
31    #[inline(always)]
32    pub fn is_utmi(&self) -> bool {
33        *self == ULPI_BYPASS_ENABLE_A::UTMI
34    }
35    #[doc = "Enable ULPI interface, disable UTMI interface"]
36    #[inline(always)]
37    pub fn is_ulpi(&self) -> bool {
38        *self == ULPI_BYPASS_ENABLE_A::ULPI
39    }
40}
41#[doc = "Field `ulpi_bypass_enable` writer - ULPI bypass enable"]
42pub type ULPI_BYPASS_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, ULPI_BYPASS_ENABLE_A>;
43impl<'a, REG> ULPI_BYPASS_ENABLE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Enable UTMI interface, disable ULPI interface"]
48    #[inline(always)]
49    pub fn utmi(self) -> &'a mut crate::W<REG> {
50        self.variant(ULPI_BYPASS_ENABLE_A::UTMI)
51    }
52    #[doc = "Enable ULPI interface, disable UTMI interface"]
53    #[inline(always)]
54    pub fn ulpi(self) -> &'a mut crate::W<REG> {
55        self.variant(ULPI_BYPASS_ENABLE_A::ULPI)
56    }
57}
58#[doc = "Field `ahb_master_interface_incrx_align_enable` reader - Master interface INCRX align enable"]
59pub type AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_R =
60    crate::BitReader<AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A>;
61#[doc = "Master interface INCRX align enable\n\nValue on reset: 0"]
62#[derive(Clone, Copy, Debug, PartialEq, Eq)]
63pub enum AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A {
64    #[doc = "1: Start INCRx burst only on burst x-align address"]
65    BURST_X_ALIGN_ADDRESS = 1,
66    #[doc = "0: Start burst on any double word boundary Note: This bit must enable if any bit of bit\\[11:9\\] is enabled"]
67    ANY_DOUBLE_WORD_BOUNDARY = 0,
68}
69impl From<AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A> for bool {
70    #[inline(always)]
71    fn from(variant: AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A) -> Self {
72        variant as u8 != 0
73    }
74}
75impl AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_R {
76    #[doc = "Get enumerated values variant"]
77    #[inline(always)]
78    pub const fn variant(&self) -> AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A {
79        match self.bits {
80            true => AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A::BURST_X_ALIGN_ADDRESS,
81            false => AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A::ANY_DOUBLE_WORD_BOUNDARY,
82        }
83    }
84    #[doc = "Start INCRx burst only on burst x-align address"]
85    #[inline(always)]
86    pub fn is_burst_x_align_address(&self) -> bool {
87        *self == AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A::BURST_X_ALIGN_ADDRESS
88    }
89    #[doc = "Start burst on any double word boundary Note: This bit must enable if any bit of bit\\[11:9\\] is enabled"]
90    #[inline(always)]
91    pub fn is_any_double_word_boundary(&self) -> bool {
92        *self == AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A::ANY_DOUBLE_WORD_BOUNDARY
93    }
94}
95#[doc = "Field `ahb_master_interface_incrx_align_enable` writer - Master interface INCRX align enable"]
96pub type AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_W<'a, REG> =
97    crate::BitWriter<'a, REG, AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A>;
98impl<'a, REG> AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_W<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Start INCRx burst only on burst x-align address"]
103    #[inline(always)]
104    pub fn burst_x_align_address(self) -> &'a mut crate::W<REG> {
105        self.variant(AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A::BURST_X_ALIGN_ADDRESS)
106    }
107    #[doc = "Start burst on any double word boundary Note: This bit must enable if any bit of bit\\[11:9\\] is enabled"]
108    #[inline(always)]
109    pub fn any_double_word_boundary(self) -> &'a mut crate::W<REG> {
110        self.variant(AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_A::ANY_DOUBLE_WORD_BOUNDARY)
111    }
112}
113#[doc = "Field `ahb_master_interface_burst_type_incr4_enable` reader - Master interface burst type INCR4 enable"]
114pub type AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_R =
115    crate::BitReader<AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A>;
116#[doc = "Master interface burst type INCR4 enable\n\nValue on reset: 0"]
117#[derive(Clone, Copy, Debug, PartialEq, Eq)]
118pub enum AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A {
119    #[doc = "1: Use INCR4 when appropriate"]
120    USE_INCR4 = 1,
121    #[doc = "0: Do not use INCR4, use other enabled INCRX or unspecified length burst INCR"]
122    NOT_USE_INCR4 = 0,
123}
124impl From<AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A> for bool {
125    #[inline(always)]
126    fn from(variant: AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A) -> Self {
127        variant as u8 != 0
128    }
129}
130impl AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_R {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A {
134        match self.bits {
135            true => AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A::USE_INCR4,
136            false => AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A::NOT_USE_INCR4,
137        }
138    }
139    #[doc = "Use INCR4 when appropriate"]
140    #[inline(always)]
141    pub fn is_use_incr4(&self) -> bool {
142        *self == AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A::USE_INCR4
143    }
144    #[doc = "Do not use INCR4, use other enabled INCRX or unspecified length burst INCR"]
145    #[inline(always)]
146    pub fn is_not_use_incr4(&self) -> bool {
147        *self == AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A::NOT_USE_INCR4
148    }
149}
150#[doc = "Field `ahb_master_interface_burst_type_incr4_enable` writer - Master interface burst type INCR4 enable"]
151pub type AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_W<'a, REG> =
152    crate::BitWriter<'a, REG, AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A>;
153impl<'a, REG> AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156{
157    #[doc = "Use INCR4 when appropriate"]
158    #[inline(always)]
159    pub fn use_incr4(self) -> &'a mut crate::W<REG> {
160        self.variant(AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A::USE_INCR4)
161    }
162    #[doc = "Do not use INCR4, use other enabled INCRX or unspecified length burst INCR"]
163    #[inline(always)]
164    pub fn not_use_incr4(self) -> &'a mut crate::W<REG> {
165        self.variant(AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_A::NOT_USE_INCR4)
166    }
167}
168#[doc = "Field `ahb_master_interface_incr8_enable` reader - Master interface INCR8 enable"]
169pub type AHB_MASTER_INTERFACE_INCR8_ENABLE_R =
170    crate::BitReader<AHB_MASTER_INTERFACE_INCR8_ENABLE_A>;
171#[doc = "Master interface INCR8 enable\n\nValue on reset: 0"]
172#[derive(Clone, Copy, Debug, PartialEq, Eq)]
173pub enum AHB_MASTER_INTERFACE_INCR8_ENABLE_A {
174    #[doc = "1: Use INCR8 when appropriate"]
175    USE_INCR8 = 1,
176    #[doc = "0: Do not use INCR8, use other enabled INCRX or unspecified length burst INCR"]
177    NOT_USE_INCR8 = 0,
178}
179impl From<AHB_MASTER_INTERFACE_INCR8_ENABLE_A> for bool {
180    #[inline(always)]
181    fn from(variant: AHB_MASTER_INTERFACE_INCR8_ENABLE_A) -> Self {
182        variant as u8 != 0
183    }
184}
185impl AHB_MASTER_INTERFACE_INCR8_ENABLE_R {
186    #[doc = "Get enumerated values variant"]
187    #[inline(always)]
188    pub const fn variant(&self) -> AHB_MASTER_INTERFACE_INCR8_ENABLE_A {
189        match self.bits {
190            true => AHB_MASTER_INTERFACE_INCR8_ENABLE_A::USE_INCR8,
191            false => AHB_MASTER_INTERFACE_INCR8_ENABLE_A::NOT_USE_INCR8,
192        }
193    }
194    #[doc = "Use INCR8 when appropriate"]
195    #[inline(always)]
196    pub fn is_use_incr8(&self) -> bool {
197        *self == AHB_MASTER_INTERFACE_INCR8_ENABLE_A::USE_INCR8
198    }
199    #[doc = "Do not use INCR8, use other enabled INCRX or unspecified length burst INCR"]
200    #[inline(always)]
201    pub fn is_not_use_incr8(&self) -> bool {
202        *self == AHB_MASTER_INTERFACE_INCR8_ENABLE_A::NOT_USE_INCR8
203    }
204}
205#[doc = "Field `ahb_master_interface_incr8_enable` writer - Master interface INCR8 enable"]
206pub type AHB_MASTER_INTERFACE_INCR8_ENABLE_W<'a, REG> =
207    crate::BitWriter<'a, REG, AHB_MASTER_INTERFACE_INCR8_ENABLE_A>;
208impl<'a, REG> AHB_MASTER_INTERFACE_INCR8_ENABLE_W<'a, REG>
209where
210    REG: crate::Writable + crate::RegisterSpec,
211{
212    #[doc = "Use INCR8 when appropriate"]
213    #[inline(always)]
214    pub fn use_incr8(self) -> &'a mut crate::W<REG> {
215        self.variant(AHB_MASTER_INTERFACE_INCR8_ENABLE_A::USE_INCR8)
216    }
217    #[doc = "Do not use INCR8, use other enabled INCRX or unspecified length burst INCR"]
218    #[inline(always)]
219    pub fn not_use_incr8(self) -> &'a mut crate::W<REG> {
220        self.variant(AHB_MASTER_INTERFACE_INCR8_ENABLE_A::NOT_USE_INCR8)
221    }
222}
223#[doc = "Field `ahb_master_interface_incr16_enable` reader - Master interface INCR16 enable"]
224pub type AHB_MASTER_INTERFACE_INCR16_ENABLE_R =
225    crate::BitReader<AHB_MASTER_INTERFACE_INCR16_ENABLE_A>;
226#[doc = "Master interface INCR16 enable\n\nValue on reset: 0"]
227#[derive(Clone, Copy, Debug, PartialEq, Eq)]
228pub enum AHB_MASTER_INTERFACE_INCR16_ENABLE_A {
229    #[doc = "1: Use INCR16 when appropriate"]
230    USE_INCR16 = 1,
231    #[doc = "0: Do not use INCR16, use other enabled INCRX or unspecified length burst INCR"]
232    NOT_USE_INCR16 = 0,
233}
234impl From<AHB_MASTER_INTERFACE_INCR16_ENABLE_A> for bool {
235    #[inline(always)]
236    fn from(variant: AHB_MASTER_INTERFACE_INCR16_ENABLE_A) -> Self {
237        variant as u8 != 0
238    }
239}
240impl AHB_MASTER_INTERFACE_INCR16_ENABLE_R {
241    #[doc = "Get enumerated values variant"]
242    #[inline(always)]
243    pub const fn variant(&self) -> AHB_MASTER_INTERFACE_INCR16_ENABLE_A {
244        match self.bits {
245            true => AHB_MASTER_INTERFACE_INCR16_ENABLE_A::USE_INCR16,
246            false => AHB_MASTER_INTERFACE_INCR16_ENABLE_A::NOT_USE_INCR16,
247        }
248    }
249    #[doc = "Use INCR16 when appropriate"]
250    #[inline(always)]
251    pub fn is_use_incr16(&self) -> bool {
252        *self == AHB_MASTER_INTERFACE_INCR16_ENABLE_A::USE_INCR16
253    }
254    #[doc = "Do not use INCR16, use other enabled INCRX or unspecified length burst INCR"]
255    #[inline(always)]
256    pub fn is_not_use_incr16(&self) -> bool {
257        *self == AHB_MASTER_INTERFACE_INCR16_ENABLE_A::NOT_USE_INCR16
258    }
259}
260#[doc = "Field `ahb_master_interface_incr16_enable` writer - Master interface INCR16 enable"]
261pub type AHB_MASTER_INTERFACE_INCR16_ENABLE_W<'a, REG> =
262    crate::BitWriter<'a, REG, AHB_MASTER_INTERFACE_INCR16_ENABLE_A>;
263impl<'a, REG> AHB_MASTER_INTERFACE_INCR16_ENABLE_W<'a, REG>
264where
265    REG: crate::Writable + crate::RegisterSpec,
266{
267    #[doc = "Use INCR16 when appropriate"]
268    #[inline(always)]
269    pub fn use_incr16(self) -> &'a mut crate::W<REG> {
270        self.variant(AHB_MASTER_INTERFACE_INCR16_ENABLE_A::USE_INCR16)
271    }
272    #[doc = "Do not use INCR16, use other enabled INCRX or unspecified length burst INCR"]
273    #[inline(always)]
274    pub fn not_use_incr16(self) -> &'a mut crate::W<REG> {
275        self.variant(AHB_MASTER_INTERFACE_INCR16_ENABLE_A::NOT_USE_INCR16)
276    }
277}
278#[doc = "Field `pp2vbus` reader - "]
279pub type PP2VBUS_R = crate::BitReader<PP2VBUS_A>;
280#[doc = "\n\nValue on reset: 0"]
281#[derive(Clone, Copy, Debug, PartialEq, Eq)]
282pub enum PP2VBUS_A {
283    #[doc = "1: ULPI wrapper interface will automatically set or clear DrvVbus register in ULPI PHY according to the port power status form the root hub"]
284    AUTO = 1,
285    #[doc = "0: ULPI wrapper will ignore the difference between power status of root hub and ULPI PHY"]
286    IGNORE = 0,
287}
288impl From<PP2VBUS_A> for bool {
289    #[inline(always)]
290    fn from(variant: PP2VBUS_A) -> Self {
291        variant as u8 != 0
292    }
293}
294impl PP2VBUS_R {
295    #[doc = "Get enumerated values variant"]
296    #[inline(always)]
297    pub const fn variant(&self) -> PP2VBUS_A {
298        match self.bits {
299            true => PP2VBUS_A::AUTO,
300            false => PP2VBUS_A::IGNORE,
301        }
302    }
303    #[doc = "ULPI wrapper interface will automatically set or clear DrvVbus register in ULPI PHY according to the port power status form the root hub"]
304    #[inline(always)]
305    pub fn is_auto(&self) -> bool {
306        *self == PP2VBUS_A::AUTO
307    }
308    #[doc = "ULPI wrapper will ignore the difference between power status of root hub and ULPI PHY"]
309    #[inline(always)]
310    pub fn is_ignore(&self) -> bool {
311        *self == PP2VBUS_A::IGNORE
312    }
313}
314#[doc = "Field `pp2vbus` writer - "]
315pub type PP2VBUS_W<'a, REG> = crate::BitWriter<'a, REG, PP2VBUS_A>;
316impl<'a, REG> PP2VBUS_W<'a, REG>
317where
318    REG: crate::Writable + crate::RegisterSpec,
319{
320    #[doc = "ULPI wrapper interface will automatically set or clear DrvVbus register in ULPI PHY according to the port power status form the root hub"]
321    #[inline(always)]
322    pub fn auto(self) -> &'a mut crate::W<REG> {
323        self.variant(PP2VBUS_A::AUTO)
324    }
325    #[doc = "ULPI wrapper will ignore the difference between power status of root hub and ULPI PHY"]
326    #[inline(always)]
327    pub fn ignore(self) -> &'a mut crate::W<REG> {
328        self.variant(PP2VBUS_A::IGNORE)
329    }
330}
331#[doc = "Field `resume_k_to_se0_transition` reader - "]
332pub type RESUME_K_TO_SE0_TRANSITION_R = crate::BitReader<RESUME_K_TO_SE0_TRANSITION_A>;
333#[doc = "\n\nValue on reset: 0"]
334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
335pub enum RESUME_K_TO_SE0_TRANSITION_A {
336    #[doc = "1: Within 2 us of the resume-K to SE0 transition"]
337    WITHIN_2US = 1,
338    #[doc = "0: Random time value of the resume-K to SE0 transition"]
339    RANDOM = 0,
340}
341impl From<RESUME_K_TO_SE0_TRANSITION_A> for bool {
342    #[inline(always)]
343    fn from(variant: RESUME_K_TO_SE0_TRANSITION_A) -> Self {
344        variant as u8 != 0
345    }
346}
347impl RESUME_K_TO_SE0_TRANSITION_R {
348    #[doc = "Get enumerated values variant"]
349    #[inline(always)]
350    pub const fn variant(&self) -> RESUME_K_TO_SE0_TRANSITION_A {
351        match self.bits {
352            true => RESUME_K_TO_SE0_TRANSITION_A::WITHIN_2US,
353            false => RESUME_K_TO_SE0_TRANSITION_A::RANDOM,
354        }
355    }
356    #[doc = "Within 2 us of the resume-K to SE0 transition"]
357    #[inline(always)]
358    pub fn is_within_2us(&self) -> bool {
359        *self == RESUME_K_TO_SE0_TRANSITION_A::WITHIN_2US
360    }
361    #[doc = "Random time value of the resume-K to SE0 transition"]
362    #[inline(always)]
363    pub fn is_random(&self) -> bool {
364        *self == RESUME_K_TO_SE0_TRANSITION_A::RANDOM
365    }
366}
367#[doc = "Field `resume_k_to_se0_transition` writer - "]
368pub type RESUME_K_TO_SE0_TRANSITION_W<'a, REG> =
369    crate::BitWriter<'a, REG, RESUME_K_TO_SE0_TRANSITION_A>;
370impl<'a, REG> RESUME_K_TO_SE0_TRANSITION_W<'a, REG>
371where
372    REG: crate::Writable + crate::RegisterSpec,
373{
374    #[doc = "Within 2 us of the resume-K to SE0 transition"]
375    #[inline(always)]
376    pub fn within_2us(self) -> &'a mut crate::W<REG> {
377        self.variant(RESUME_K_TO_SE0_TRANSITION_A::WITHIN_2US)
378    }
379    #[doc = "Random time value of the resume-K to SE0 transition"]
380    #[inline(always)]
381    pub fn random(self) -> &'a mut crate::W<REG> {
382        self.variant(RESUME_K_TO_SE0_TRANSITION_A::RANDOM)
383    }
384}
385#[doc = "Field `ohci_count_select` reader - OHCI count select"]
386pub type OHCI_COUNT_SELECT_R = crate::BitReader<OHCI_COUNT_SELECT_A>;
387#[doc = "OHCI count select\n\nValue on reset: 0"]
388#[derive(Clone, Copy, Debug, PartialEq, Eq)]
389pub enum OHCI_COUNT_SELECT_A {
390    #[doc = "1: Simulation mode. The counters will be much shorter then real time"]
391    SIMULATION = 1,
392    #[doc = "0: Normal mode. The counters will count full time"]
393    NORMAL = 0,
394}
395impl From<OHCI_COUNT_SELECT_A> for bool {
396    #[inline(always)]
397    fn from(variant: OHCI_COUNT_SELECT_A) -> Self {
398        variant as u8 != 0
399    }
400}
401impl OHCI_COUNT_SELECT_R {
402    #[doc = "Get enumerated values variant"]
403    #[inline(always)]
404    pub const fn variant(&self) -> OHCI_COUNT_SELECT_A {
405        match self.bits {
406            true => OHCI_COUNT_SELECT_A::SIMULATION,
407            false => OHCI_COUNT_SELECT_A::NORMAL,
408        }
409    }
410    #[doc = "Simulation mode. The counters will be much shorter then real time"]
411    #[inline(always)]
412    pub fn is_simulation(&self) -> bool {
413        *self == OHCI_COUNT_SELECT_A::SIMULATION
414    }
415    #[doc = "Normal mode. The counters will count full time"]
416    #[inline(always)]
417    pub fn is_normal(&self) -> bool {
418        *self == OHCI_COUNT_SELECT_A::NORMAL
419    }
420}
421#[doc = "Field `ohci_count_select` writer - OHCI count select"]
422pub type OHCI_COUNT_SELECT_W<'a, REG> = crate::BitWriter<'a, REG, OHCI_COUNT_SELECT_A>;
423impl<'a, REG> OHCI_COUNT_SELECT_W<'a, REG>
424where
425    REG: crate::Writable + crate::RegisterSpec,
426{
427    #[doc = "Simulation mode. The counters will be much shorter then real time"]
428    #[inline(always)]
429    pub fn simulation(self) -> &'a mut crate::W<REG> {
430        self.variant(OHCI_COUNT_SELECT_A::SIMULATION)
431    }
432    #[doc = "Normal mode. The counters will count full time"]
433    #[inline(always)]
434    pub fn normal(self) -> &'a mut crate::W<REG> {
435        self.variant(OHCI_COUNT_SELECT_A::NORMAL)
436    }
437}
438#[doc = "Field `dma_transfer_status_enable` reader - DMA Transfer Status Enable"]
439pub type DMA_TRANSFER_STATUS_ENABLE_R = crate::BitReader<DMA_TRANSFER_STATUS_ENABLE_A>;
440#[doc = "DMA Transfer Status Enable\n\nValue on reset: 1"]
441#[derive(Clone, Copy, Debug, PartialEq, Eq)]
442pub enum DMA_TRANSFER_STATUS_ENABLE_A {
443    #[doc = "0: Disable"]
444    DISABLE = 0,
445    #[doc = "1: Enable"]
446    ENABLE = 1,
447}
448impl From<DMA_TRANSFER_STATUS_ENABLE_A> for bool {
449    #[inline(always)]
450    fn from(variant: DMA_TRANSFER_STATUS_ENABLE_A) -> Self {
451        variant as u8 != 0
452    }
453}
454impl DMA_TRANSFER_STATUS_ENABLE_R {
455    #[doc = "Get enumerated values variant"]
456    #[inline(always)]
457    pub const fn variant(&self) -> DMA_TRANSFER_STATUS_ENABLE_A {
458        match self.bits {
459            false => DMA_TRANSFER_STATUS_ENABLE_A::DISABLE,
460            true => DMA_TRANSFER_STATUS_ENABLE_A::ENABLE,
461        }
462    }
463    #[doc = "Disable"]
464    #[inline(always)]
465    pub fn is_disable(&self) -> bool {
466        *self == DMA_TRANSFER_STATUS_ENABLE_A::DISABLE
467    }
468    #[doc = "Enable"]
469    #[inline(always)]
470    pub fn is_enable(&self) -> bool {
471        *self == DMA_TRANSFER_STATUS_ENABLE_A::ENABLE
472    }
473}
474impl R {
475    #[doc = "Bit 0 - ULPI bypass enable"]
476    #[inline(always)]
477    pub fn ulpi_bypass_enable(&self) -> ULPI_BYPASS_ENABLE_R {
478        ULPI_BYPASS_ENABLE_R::new((self.bits & 1) != 0)
479    }
480    #[doc = "Bit 8 - Master interface INCRX align enable"]
481    #[inline(always)]
482    pub fn ahb_master_interface_incrx_align_enable(
483        &self,
484    ) -> AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_R {
485        AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_R::new(((self.bits >> 8) & 1) != 0)
486    }
487    #[doc = "Bit 9 - Master interface burst type INCR4 enable"]
488    #[inline(always)]
489    pub fn ahb_master_interface_burst_type_incr4_enable(
490        &self,
491    ) -> AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_R {
492        AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_R::new(((self.bits >> 9) & 1) != 0)
493    }
494    #[doc = "Bit 10 - Master interface INCR8 enable"]
495    #[inline(always)]
496    pub fn ahb_master_interface_incr8_enable(&self) -> AHB_MASTER_INTERFACE_INCR8_ENABLE_R {
497        AHB_MASTER_INTERFACE_INCR8_ENABLE_R::new(((self.bits >> 10) & 1) != 0)
498    }
499    #[doc = "Bit 11 - Master interface INCR16 enable"]
500    #[inline(always)]
501    pub fn ahb_master_interface_incr16_enable(&self) -> AHB_MASTER_INTERFACE_INCR16_ENABLE_R {
502        AHB_MASTER_INTERFACE_INCR16_ENABLE_R::new(((self.bits >> 11) & 1) != 0)
503    }
504    #[doc = "Bit 12"]
505    #[inline(always)]
506    pub fn pp2vbus(&self) -> PP2VBUS_R {
507        PP2VBUS_R::new(((self.bits >> 12) & 1) != 0)
508    }
509    #[doc = "Bit 18"]
510    #[inline(always)]
511    pub fn resume_k_to_se0_transition(&self) -> RESUME_K_TO_SE0_TRANSITION_R {
512        RESUME_K_TO_SE0_TRANSITION_R::new(((self.bits >> 18) & 1) != 0)
513    }
514    #[doc = "Bit 25 - OHCI count select"]
515    #[inline(always)]
516    pub fn ohci_count_select(&self) -> OHCI_COUNT_SELECT_R {
517        OHCI_COUNT_SELECT_R::new(((self.bits >> 25) & 1) != 0)
518    }
519    #[doc = "Bit 28 - DMA Transfer Status Enable"]
520    #[inline(always)]
521    pub fn dma_transfer_status_enable(&self) -> DMA_TRANSFER_STATUS_ENABLE_R {
522        DMA_TRANSFER_STATUS_ENABLE_R::new(((self.bits >> 28) & 1) != 0)
523    }
524}
525impl W {
526    #[doc = "Bit 0 - ULPI bypass enable"]
527    #[inline(always)]
528    #[must_use]
529    pub fn ulpi_bypass_enable(&mut self) -> ULPI_BYPASS_ENABLE_W<HCI_INTERFACE_SPEC> {
530        ULPI_BYPASS_ENABLE_W::new(self, 0)
531    }
532    #[doc = "Bit 8 - Master interface INCRX align enable"]
533    #[inline(always)]
534    #[must_use]
535    pub fn ahb_master_interface_incrx_align_enable(
536        &mut self,
537    ) -> AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_W<HCI_INTERFACE_SPEC> {
538        AHB_MASTER_INTERFACE_INCRX_ALIGN_ENABLE_W::new(self, 8)
539    }
540    #[doc = "Bit 9 - Master interface burst type INCR4 enable"]
541    #[inline(always)]
542    #[must_use]
543    pub fn ahb_master_interface_burst_type_incr4_enable(
544        &mut self,
545    ) -> AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_W<HCI_INTERFACE_SPEC> {
546        AHB_MASTER_INTERFACE_BURST_TYPE_INCR4_ENABLE_W::new(self, 9)
547    }
548    #[doc = "Bit 10 - Master interface INCR8 enable"]
549    #[inline(always)]
550    #[must_use]
551    pub fn ahb_master_interface_incr8_enable(
552        &mut self,
553    ) -> AHB_MASTER_INTERFACE_INCR8_ENABLE_W<HCI_INTERFACE_SPEC> {
554        AHB_MASTER_INTERFACE_INCR8_ENABLE_W::new(self, 10)
555    }
556    #[doc = "Bit 11 - Master interface INCR16 enable"]
557    #[inline(always)]
558    #[must_use]
559    pub fn ahb_master_interface_incr16_enable(
560        &mut self,
561    ) -> AHB_MASTER_INTERFACE_INCR16_ENABLE_W<HCI_INTERFACE_SPEC> {
562        AHB_MASTER_INTERFACE_INCR16_ENABLE_W::new(self, 11)
563    }
564    #[doc = "Bit 12"]
565    #[inline(always)]
566    #[must_use]
567    pub fn pp2vbus(&mut self) -> PP2VBUS_W<HCI_INTERFACE_SPEC> {
568        PP2VBUS_W::new(self, 12)
569    }
570    #[doc = "Bit 18"]
571    #[inline(always)]
572    #[must_use]
573    pub fn resume_k_to_se0_transition(
574        &mut self,
575    ) -> RESUME_K_TO_SE0_TRANSITION_W<HCI_INTERFACE_SPEC> {
576        RESUME_K_TO_SE0_TRANSITION_W::new(self, 18)
577    }
578    #[doc = "Bit 25 - OHCI count select"]
579    #[inline(always)]
580    #[must_use]
581    pub fn ohci_count_select(&mut self) -> OHCI_COUNT_SELECT_W<HCI_INTERFACE_SPEC> {
582        OHCI_COUNT_SELECT_W::new(self, 25)
583    }
584    #[doc = r" Writes raw bits to the register."]
585    #[doc = r""]
586    #[doc = r" # Safety"]
587    #[doc = r""]
588    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
589    #[inline(always)]
590    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
591        self.bits = bits;
592        self
593    }
594}
595#[doc = "HCI Interface Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hci_interface::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hci_interface::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
596pub struct HCI_INTERFACE_SPEC;
597impl crate::RegisterSpec for HCI_INTERFACE_SPEC {
598    type Ux = u32;
599}
600#[doc = "`read()` method returns [`hci_interface::R`](R) reader structure"]
601impl crate::Readable for HCI_INTERFACE_SPEC {}
602#[doc = "`write(|w| ..)` method takes [`hci_interface::W`](W) writer structure"]
603impl crate::Writable for HCI_INTERFACE_SPEC {
604    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
605    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
606}
607#[doc = "`reset()` method sets hci_interface to value 0x1000_0000"]
608impl crate::Resettable for HCI_INTERFACE_SPEC {
609    const RESET_VALUE: Self::Ux = 0x1000_0000;
610}
d1_pac/usb1/hci_controller_phy_interface/hci_interface.rs

d1_pac/usb1/hci_controller_phy_interface/
hci_interface.rs
