d1_pac/usb1/ehci_operational/
usbsts.rs

1#[doc = "Register `usbsts` reader"]
2pub type R = crate::R<USBSTS_SPEC>;
3#[doc = "Register `usbsts` writer"]
4pub type W = crate::W<USBSTS_SPEC>;
5#[doc = "Field `usbint` reader - USB Interrupt(USBINT) The Host Controller sets this bit to a one on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes)"]
6pub type USBINT_R = crate::BitReader;
7#[doc = "Field `usbint` writer - USB Interrupt(USBINT) The Host Controller sets this bit to a one on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes)"]
8pub type USBINT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `usberrint` reader - USB Error Interrupt(USBERRINT)\n\nThe Host Controller sets this bit to 1 when completion of USB transaction results in an error condition(e.g. error counter underflow).If the TD on which the error interrupt occurred also had its IOC bit set, both. This bit and USBINT bit are set."]
10pub type USBERRINT_R = crate::BitReader;
11#[doc = "Field `usberrint` writer - USB Error Interrupt(USBERRINT)\n\nThe Host Controller sets this bit to 1 when completion of USB transaction results in an error condition(e.g. error counter underflow).If the TD on which the error interrupt occurred also had its IOC bit set, both. This bit and USBINT bit are set."]
12pub type USBERRINT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `port_change_detect` reader - Port Change Detect\n\nThe Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Chang being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit."]
14pub type PORT_CHANGE_DETECT_R = crate::BitReader;
15#[doc = "Field `port_change_detect` writer - Port Change Detect\n\nThe Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Chang being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit."]
16pub type PORT_CHANGE_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `frame_list_rollover` reader - Frame List Rollover\n\nThe Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size is 1024, the Frame Index Register rolls over every time FRINDEX \\[13\\] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX \\[12\\] toggles."]
18pub type FRAME_LIST_ROLLOVER_R = crate::BitReader;
19#[doc = "Field `frame_list_rollover` writer - Frame List Rollover\n\nThe Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size is 1024, the Frame Index Register rolls over every time FRINDEX \\[13\\] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX \\[12\\] toggles."]
20pub type FRAME_LIST_ROLLOVER_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `host_system_error` reader - Host System Error\n\nThe Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs."]
22pub type HOST_SYSTEM_ERROR_R = crate::BitReader;
23#[doc = "Field `host_system_error` writer - Host System Error\n\nThe Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs."]
24pub type HOST_SYSTEM_ERROR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `interrupt_on_async_advance` reader - Interrupt on Async Advance\n\nSystem software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
26pub type INTERRUPT_ON_ASYNC_ADVANCE_R = crate::BitReader;
27#[doc = "Field `interrupt_on_async_advance` writer - Interrupt on Async Advance\n\nSystem software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
28pub type INTERRUPT_ON_ASYNC_ADVANCE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `hc_halted` reader - HC Halted\n\nThis bit is a zero whenever the Run/Stop bit is a one. The Host Controller Sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller Hardware (e.g. internal error).\n\nThe default value is '1'"]
30pub type HC_HALTED_R = crate::BitReader;
31#[doc = "Field `reclamation` reader - Reclamation\n\nThis is a read-only status bit, which is used to detect an empty asynchronous schedule."]
32pub type RECLAMATION_R = crate::BitReader;
33#[doc = "Field `periodic_schedule_status` reader - Periodic Schedule Status\n\nThe bit reports the current real status of the Periodic Schedule. If this bit is a zero then the status of the Periodic Schedule is disabled. If this bit is a one then the status of the Periodic Schedule is enabled. The Host Controller is not required to disable or enable the Periodic Schedule when software transitions the bit in the USBCMD register. When this bit and the bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0)."]
34pub type PERIODIC_SCHEDULE_STATUS_R = crate::BitReader;
35#[doc = "Field `asynchronous_schedule_status` reader - Asynchronous Schedule Status\n\nThe bit reports the current real status of Asynchronous Schedule. If this bit is a zero then the status of the Asynchronous Schedule is disabled. If this bit is a one then the status of the Asynchronous Schedule is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0)."]
36pub type ASYNCHRONOUS_SCHEDULE_STATUS_R = crate::BitReader;
37impl R {
38    #[doc = "Bit 0 - USB Interrupt(USBINT) The Host Controller sets this bit to a one on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes)"]
39    #[inline(always)]
40    pub fn usbint(&self) -> USBINT_R {
41        USBINT_R::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1 - USB Error Interrupt(USBERRINT)\n\nThe Host Controller sets this bit to 1 when completion of USB transaction results in an error condition(e.g. error counter underflow).If the TD on which the error interrupt occurred also had its IOC bit set, both. This bit and USBINT bit are set."]
44    #[inline(always)]
45    pub fn usberrint(&self) -> USBERRINT_R {
46        USBERRINT_R::new(((self.bits >> 1) & 1) != 0)
47    }
48    #[doc = "Bit 2 - Port Change Detect\n\nThe Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Chang being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit."]
49    #[inline(always)]
50    pub fn port_change_detect(&self) -> PORT_CHANGE_DETECT_R {
51        PORT_CHANGE_DETECT_R::new(((self.bits >> 2) & 1) != 0)
52    }
53    #[doc = "Bit 3 - Frame List Rollover\n\nThe Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size is 1024, the Frame Index Register rolls over every time FRINDEX \\[13\\] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX \\[12\\] toggles."]
54    #[inline(always)]
55    pub fn frame_list_rollover(&self) -> FRAME_LIST_ROLLOVER_R {
56        FRAME_LIST_ROLLOVER_R::new(((self.bits >> 3) & 1) != 0)
57    }
58    #[doc = "Bit 4 - Host System Error\n\nThe Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs."]
59    #[inline(always)]
60    pub fn host_system_error(&self) -> HOST_SYSTEM_ERROR_R {
61        HOST_SYSTEM_ERROR_R::new(((self.bits >> 4) & 1) != 0)
62    }
63    #[doc = "Bit 5 - Interrupt on Async Advance\n\nSystem software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
64    #[inline(always)]
65    pub fn interrupt_on_async_advance(&self) -> INTERRUPT_ON_ASYNC_ADVANCE_R {
66        INTERRUPT_ON_ASYNC_ADVANCE_R::new(((self.bits >> 5) & 1) != 0)
67    }
68    #[doc = "Bit 12 - HC Halted\n\nThis bit is a zero whenever the Run/Stop bit is a one. The Host Controller Sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller Hardware (e.g. internal error).\n\nThe default value is '1'"]
69    #[inline(always)]
70    pub fn hc_halted(&self) -> HC_HALTED_R {
71        HC_HALTED_R::new(((self.bits >> 12) & 1) != 0)
72    }
73    #[doc = "Bit 13 - Reclamation\n\nThis is a read-only status bit, which is used to detect an empty asynchronous schedule."]
74    #[inline(always)]
75    pub fn reclamation(&self) -> RECLAMATION_R {
76        RECLAMATION_R::new(((self.bits >> 13) & 1) != 0)
77    }
78    #[doc = "Bit 14 - Periodic Schedule Status\n\nThe bit reports the current real status of the Periodic Schedule. If this bit is a zero then the status of the Periodic Schedule is disabled. If this bit is a one then the status of the Periodic Schedule is enabled. The Host Controller is not required to disable or enable the Periodic Schedule when software transitions the bit in the USBCMD register. When this bit and the bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0)."]
79    #[inline(always)]
80    pub fn periodic_schedule_status(&self) -> PERIODIC_SCHEDULE_STATUS_R {
81        PERIODIC_SCHEDULE_STATUS_R::new(((self.bits >> 14) & 1) != 0)
82    }
83    #[doc = "Bit 15 - Asynchronous Schedule Status\n\nThe bit reports the current real status of Asynchronous Schedule. If this bit is a zero then the status of the Asynchronous Schedule is disabled. If this bit is a one then the status of the Asynchronous Schedule is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0)."]
84    #[inline(always)]
85    pub fn asynchronous_schedule_status(&self) -> ASYNCHRONOUS_SCHEDULE_STATUS_R {
86        ASYNCHRONOUS_SCHEDULE_STATUS_R::new(((self.bits >> 15) & 1) != 0)
87    }
88}
89impl W {
90    #[doc = "Bit 0 - USB Interrupt(USBINT) The Host Controller sets this bit to a one on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes)"]
91    #[inline(always)]
92    #[must_use]
93    pub fn usbint(&mut self) -> USBINT_W<USBSTS_SPEC> {
94        USBINT_W::new(self, 0)
95    }
96    #[doc = "Bit 1 - USB Error Interrupt(USBERRINT)\n\nThe Host Controller sets this bit to 1 when completion of USB transaction results in an error condition(e.g. error counter underflow).If the TD on which the error interrupt occurred also had its IOC bit set, both. This bit and USBINT bit are set."]
97    #[inline(always)]
98    #[must_use]
99    pub fn usberrint(&mut self) -> USBERRINT_W<USBSTS_SPEC> {
100        USBERRINT_W::new(self, 1)
101    }
102    #[doc = "Bit 2 - Port Change Detect\n\nThe Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Chang being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit."]
103    #[inline(always)]
104    #[must_use]
105    pub fn port_change_detect(&mut self) -> PORT_CHANGE_DETECT_W<USBSTS_SPEC> {
106        PORT_CHANGE_DETECT_W::new(self, 2)
107    }
108    #[doc = "Bit 3 - Frame List Rollover\n\nThe Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size is 1024, the Frame Index Register rolls over every time FRINDEX \\[13\\] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX \\[12\\] toggles."]
109    #[inline(always)]
110    #[must_use]
111    pub fn frame_list_rollover(&mut self) -> FRAME_LIST_ROLLOVER_W<USBSTS_SPEC> {
112        FRAME_LIST_ROLLOVER_W::new(self, 3)
113    }
114    #[doc = "Bit 4 - Host System Error\n\nThe Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs."]
115    #[inline(always)]
116    #[must_use]
117    pub fn host_system_error(&mut self) -> HOST_SYSTEM_ERROR_W<USBSTS_SPEC> {
118        HOST_SYSTEM_ERROR_W::new(self, 4)
119    }
120    #[doc = "Bit 5 - Interrupt on Async Advance\n\nSystem software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
121    #[inline(always)]
122    #[must_use]
123    pub fn interrupt_on_async_advance(&mut self) -> INTERRUPT_ON_ASYNC_ADVANCE_W<USBSTS_SPEC> {
124        INTERRUPT_ON_ASYNC_ADVANCE_W::new(self, 5)
125    }
126    #[doc = r" Writes raw bits to the register."]
127    #[doc = r""]
128    #[doc = r" # Safety"]
129    #[doc = r""]
130    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
131    #[inline(always)]
132    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
133        self.bits = bits;
134        self
135    }
136}
137#[doc = "EHCI USB Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbsts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
138pub struct USBSTS_SPEC;
139impl crate::RegisterSpec for USBSTS_SPEC {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [`usbsts::R`](R) reader structure"]
143impl crate::Readable for USBSTS_SPEC {}
144#[doc = "`write(|w| ..)` method takes [`usbsts::W`](W) writer structure"]
145impl crate::Writable for USBSTS_SPEC {
146    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
147    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
148}
149#[doc = "`reset()` method sets usbsts to value 0x1000"]
150impl crate::Resettable for USBSTS_SPEC {
151    const RESET_VALUE: Self::Ux = 0x1000;
152}
d1_pac/usb1/ehci_operational/usbsts.rs

d1_pac/usb1/ehci_operational/
usbsts.rs
