d1_pac/usb1/ehci_operational/
usbintr.rs

1#[doc = "Register `usbintr` reader"]
2pub type R = crate::R<USBINTR_SPEC>;
3#[doc = "Register `usbintr` writer"]
4pub type W = crate::W<USBINTR_SPEC>;
5#[doc = "Field `usb_interrupt_enable` reader - USB Interrupt Enable\n\nWhen this bit is 1, and the USBINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.\n\nThe interrupt is acknowledged by software clearing the USBINT bit"]
6pub type USB_INTERRUPT_ENABLE_R = crate::BitReader;
7#[doc = "Field `usb_interrupt_enable` writer - USB Interrupt Enable\n\nWhen this bit is 1, and the USBINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.\n\nThe interrupt is acknowledged by software clearing the USBINT bit"]
8pub type USB_INTERRUPT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `usb_error_interrupt_enable` reader - USB Error Interrupt Enable\n\nWhen this bit is 1, and the USBERRINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.\n\nThe interrupt is acknowledged by software clearing the USBERRINT bit."]
10pub type USB_ERROR_INTERRUPT_ENABLE_R = crate::BitReader;
11#[doc = "Field `usb_error_interrupt_enable` writer - USB Error Interrupt Enable\n\nWhen this bit is 1, and the USBERRINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.\n\nThe interrupt is acknowledged by software clearing the USBERRINT bit."]
12pub type USB_ERROR_INTERRUPT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `port_change_interrupt_enable` reader - Port Change Interrupt Enable\n\nWhen this bit is 1, and the Port Chang Detect bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Chang Detect bit."]
14pub type PORT_CHANGE_INTERRUPT_ENABLE_R = crate::BitReader;
15#[doc = "Field `port_change_interrupt_enable` writer - Port Change Interrupt Enable\n\nWhen this bit is 1, and the Port Chang Detect bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Chang Detect bit."]
16pub type PORT_CHANGE_INTERRUPT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `frame_list_rollover_enable` reader - Frame List Rollover Enable\n\nWhen this bit is 1, and the Frame List Rollover bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit."]
18pub type FRAME_LIST_ROLLOVER_ENABLE_R = crate::BitReader;
19#[doc = "Field `frame_list_rollover_enable` writer - Frame List Rollover Enable\n\nWhen this bit is 1, and the Frame List Rollover bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit."]
20pub type FRAME_LIST_ROLLOVER_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `host_system_error_enable` reader - Host System Error Enable\n\n When this bit is 1, and the Host System Error Status bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit."]
22pub type HOST_SYSTEM_ERROR_ENABLE_R = crate::BitReader;
23#[doc = "Field `host_system_error_enable` writer - Host System Error Enable\n\n When this bit is 1, and the Host System Error Status bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit."]
24pub type HOST_SYSTEM_ERROR_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `interrupt_on_async_advance_enable` reader - Interrupt on Async Advance Enable\n\nWhen this bit is 1, and the Interrupt on Async Advance bit in the USBSTS register is 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit."]
26pub type INTERRUPT_ON_ASYNC_ADVANCE_ENABLE_R = crate::BitReader;
27#[doc = "Field `interrupt_on_async_advance_enable` writer - Interrupt on Async Advance Enable\n\nWhen this bit is 1, and the Interrupt on Async Advance bit in the USBSTS register is 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit."]
28pub type INTERRUPT_ON_ASYNC_ADVANCE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - USB Interrupt Enable\n\nWhen this bit is 1, and the USBINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.\n\nThe interrupt is acknowledged by software clearing the USBINT bit"]
31    #[inline(always)]
32    pub fn usb_interrupt_enable(&self) -> USB_INTERRUPT_ENABLE_R {
33        USB_INTERRUPT_ENABLE_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - USB Error Interrupt Enable\n\nWhen this bit is 1, and the USBERRINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.\n\nThe interrupt is acknowledged by software clearing the USBERRINT bit."]
36    #[inline(always)]
37    pub fn usb_error_interrupt_enable(&self) -> USB_ERROR_INTERRUPT_ENABLE_R {
38        USB_ERROR_INTERRUPT_ENABLE_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - Port Change Interrupt Enable\n\nWhen this bit is 1, and the Port Chang Detect bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Chang Detect bit."]
41    #[inline(always)]
42    pub fn port_change_interrupt_enable(&self) -> PORT_CHANGE_INTERRUPT_ENABLE_R {
43        PORT_CHANGE_INTERRUPT_ENABLE_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - Frame List Rollover Enable\n\nWhen this bit is 1, and the Frame List Rollover bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit."]
46    #[inline(always)]
47    pub fn frame_list_rollover_enable(&self) -> FRAME_LIST_ROLLOVER_ENABLE_R {
48        FRAME_LIST_ROLLOVER_ENABLE_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - Host System Error Enable\n\n When this bit is 1, and the Host System Error Status bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit."]
51    #[inline(always)]
52    pub fn host_system_error_enable(&self) -> HOST_SYSTEM_ERROR_ENABLE_R {
53        HOST_SYSTEM_ERROR_ENABLE_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - Interrupt on Async Advance Enable\n\nWhen this bit is 1, and the Interrupt on Async Advance bit in the USBSTS register is 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit."]
56    #[inline(always)]
57    pub fn interrupt_on_async_advance_enable(&self) -> INTERRUPT_ON_ASYNC_ADVANCE_ENABLE_R {
58        INTERRUPT_ON_ASYNC_ADVANCE_ENABLE_R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - USB Interrupt Enable\n\nWhen this bit is 1, and the USBINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.\n\nThe interrupt is acknowledged by software clearing the USBINT bit"]
63    #[inline(always)]
64    #[must_use]
65    pub fn usb_interrupt_enable(&mut self) -> USB_INTERRUPT_ENABLE_W<USBINTR_SPEC> {
66        USB_INTERRUPT_ENABLE_W::new(self, 0)
67    }
68    #[doc = "Bit 1 - USB Error Interrupt Enable\n\nWhen this bit is 1, and the USBERRINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.\n\nThe interrupt is acknowledged by software clearing the USBERRINT bit."]
69    #[inline(always)]
70    #[must_use]
71    pub fn usb_error_interrupt_enable(&mut self) -> USB_ERROR_INTERRUPT_ENABLE_W<USBINTR_SPEC> {
72        USB_ERROR_INTERRUPT_ENABLE_W::new(self, 1)
73    }
74    #[doc = "Bit 2 - Port Change Interrupt Enable\n\nWhen this bit is 1, and the Port Chang Detect bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Chang Detect bit."]
75    #[inline(always)]
76    #[must_use]
77    pub fn port_change_interrupt_enable(&mut self) -> PORT_CHANGE_INTERRUPT_ENABLE_W<USBINTR_SPEC> {
78        PORT_CHANGE_INTERRUPT_ENABLE_W::new(self, 2)
79    }
80    #[doc = "Bit 3 - Frame List Rollover Enable\n\nWhen this bit is 1, and the Frame List Rollover bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit."]
81    #[inline(always)]
82    #[must_use]
83    pub fn frame_list_rollover_enable(&mut self) -> FRAME_LIST_ROLLOVER_ENABLE_W<USBINTR_SPEC> {
84        FRAME_LIST_ROLLOVER_ENABLE_W::new(self, 3)
85    }
86    #[doc = "Bit 4 - Host System Error Enable\n\n When this bit is 1, and the Host System Error Status bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit."]
87    #[inline(always)]
88    #[must_use]
89    pub fn host_system_error_enable(&mut self) -> HOST_SYSTEM_ERROR_ENABLE_W<USBINTR_SPEC> {
90        HOST_SYSTEM_ERROR_ENABLE_W::new(self, 4)
91    }
92    #[doc = "Bit 5 - Interrupt on Async Advance Enable\n\nWhen this bit is 1, and the Interrupt on Async Advance bit in the USBSTS register is 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit."]
93    #[inline(always)]
94    #[must_use]
95    pub fn interrupt_on_async_advance_enable(
96        &mut self,
97    ) -> INTERRUPT_ON_ASYNC_ADVANCE_ENABLE_W<USBINTR_SPEC> {
98        INTERRUPT_ON_ASYNC_ADVANCE_ENABLE_W::new(self, 5)
99    }
100    #[doc = r" Writes raw bits to the register."]
101    #[doc = r""]
102    #[doc = r" # Safety"]
103    #[doc = r""]
104    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
105    #[inline(always)]
106    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
107        self.bits = bits;
108        self
109    }
110}
111#[doc = "EHCI USB Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbintr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbintr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
112pub struct USBINTR_SPEC;
113impl crate::RegisterSpec for USBINTR_SPEC {
114    type Ux = u32;
115}
116#[doc = "`read()` method returns [`usbintr::R`](R) reader structure"]
117impl crate::Readable for USBINTR_SPEC {}
118#[doc = "`write(|w| ..)` method takes [`usbintr::W`](W) writer structure"]
119impl crate::Writable for USBINTR_SPEC {
120    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
121    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
122}
123#[doc = "`reset()` method sets usbintr to value 0"]
124impl crate::Resettable for USBINTR_SPEC {
125    const RESET_VALUE: Self::Ux = 0;
126}
d1_pac/usb1/ehci_operational/usbintr.rs

d1_pac/usb1/ehci_operational/
usbintr.rs
