d1_pac/usb1/ehci_operational/
usbcmd.rs

1#[doc = "Register `usbcmd` reader"]
2pub type R = crate::R<USBCMD_SPEC>;
3#[doc = "Register `usbcmd` writer"]
4pub type W = crate::W<USBCMD_SPEC>;
5#[doc = "Field `run_stop` reader - Run/Stop\n\nWhen set to a 1, the Host Controller proceeds with execution of the schedule. When set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears this bit. The HC Halted bit indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state.\n\nSoftware must not write a one to this field unless the Host Controller is in the Halt State. The default value is 0x0."]
6pub type RUN_STOP_R = crate::BitReader;
7#[doc = "Field `run_stop` writer - Run/Stop\n\nWhen set to a 1, the Host Controller proceeds with execution of the schedule. When set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears this bit. The HC Halted bit indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state.\n\nSoftware must not write a one to this field unless the Host Controller is in the Halt State. The default value is 0x0."]
8pub type RUN_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `host_controller_reset` reader - Host Controller Reset\n\nThis control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset.\n\nWhen software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports.\n\nAll operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s). Software must reinitialize the host controller as described in Section 4.1 of the CHEI Specification in order to return the host controller to an operational state. This bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.\n\nSoftware should not set this bit to a one when the HC Halted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
10pub type HOST_CONTROLLER_RESET_R = crate::BitReader;
11#[doc = "Field `host_controller_reset` writer - Host Controller Reset\n\nThis control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset.\n\nWhen software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports.\n\nAll operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s). Software must reinitialize the host controller as described in Section 4.1 of the CHEI Specification in order to return the host controller to an operational state. This bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.\n\nSoftware should not set this bit to a one when the HC Halted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
12pub type HOST_CONTROLLER_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `frame_list_size` reader - This field is R/W only if Programmable Frame List Flag in the HCCPARAMS register is set to one. This field specifies the size of the Frame list."]
14pub type FRAME_LIST_SIZE_R = crate::FieldReader<FRAME_LIST_SIZE_A>;
15#[doc = "This field is R/W only if Programmable Frame List Flag in the HCCPARAMS register is set to one. This field specifies the size of the Frame list.\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17#[repr(u8)]
18pub enum FRAME_LIST_SIZE_A {
19    #[doc = "0: 1024 frames"]
20    F1024 = 0,
21    #[doc = "1: 512 frames"]
22    F512 = 1,
23    #[doc = "2: 256 frames"]
24    F256 = 2,
25}
26impl From<FRAME_LIST_SIZE_A> for u8 {
27    #[inline(always)]
28    fn from(variant: FRAME_LIST_SIZE_A) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for FRAME_LIST_SIZE_A {
33    type Ux = u8;
34}
35impl FRAME_LIST_SIZE_R {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<FRAME_LIST_SIZE_A> {
39        match self.bits {
40            0 => Some(FRAME_LIST_SIZE_A::F1024),
41            1 => Some(FRAME_LIST_SIZE_A::F512),
42            2 => Some(FRAME_LIST_SIZE_A::F256),
43            _ => None,
44        }
45    }
46    #[doc = "1024 frames"]
47    #[inline(always)]
48    pub fn is_f1024(&self) -> bool {
49        *self == FRAME_LIST_SIZE_A::F1024
50    }
51    #[doc = "512 frames"]
52    #[inline(always)]
53    pub fn is_f512(&self) -> bool {
54        *self == FRAME_LIST_SIZE_A::F512
55    }
56    #[doc = "256 frames"]
57    #[inline(always)]
58    pub fn is_f256(&self) -> bool {
59        *self == FRAME_LIST_SIZE_A::F256
60    }
61}
62#[doc = "Field `frame_list_size` writer - This field is R/W only if Programmable Frame List Flag in the HCCPARAMS register is set to one. This field specifies the size of the Frame list."]
63pub type FRAME_LIST_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, FRAME_LIST_SIZE_A>;
64impl<'a, REG> FRAME_LIST_SIZE_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "1024 frames"]
70    #[inline(always)]
71    pub fn f1024(self) -> &'a mut crate::W<REG> {
72        self.variant(FRAME_LIST_SIZE_A::F1024)
73    }
74    #[doc = "512 frames"]
75    #[inline(always)]
76    pub fn f512(self) -> &'a mut crate::W<REG> {
77        self.variant(FRAME_LIST_SIZE_A::F512)
78    }
79    #[doc = "256 frames"]
80    #[inline(always)]
81    pub fn f256(self) -> &'a mut crate::W<REG> {
82        self.variant(FRAME_LIST_SIZE_A::F256)
83    }
84}
85#[doc = "Field `periodic_schedule_enable` reader - Periodic Schedule Enable\n\nThis bit controls whether the host controller skips processing the Periodic Schedule."]
86pub type PERIODIC_SCHEDULE_ENABLE_R = crate::BitReader<PERIODIC_SCHEDULE_ENABLE_A>;
87#[doc = "Periodic Schedule Enable\n\nThis bit controls whether the host controller skips processing the Periodic Schedule.\n\nValue on reset: 0"]
88#[derive(Clone, Copy, Debug, PartialEq, Eq)]
89pub enum PERIODIC_SCHEDULE_ENABLE_A {
90    #[doc = "0: Do not process the Periodic Schedule"]
91    DISABLE = 0,
92    #[doc = "1: Use the PERIODICLISTBASE register to access the Periodic Schedule"]
93    ENABLE = 1,
94}
95impl From<PERIODIC_SCHEDULE_ENABLE_A> for bool {
96    #[inline(always)]
97    fn from(variant: PERIODIC_SCHEDULE_ENABLE_A) -> Self {
98        variant as u8 != 0
99    }
100}
101impl PERIODIC_SCHEDULE_ENABLE_R {
102    #[doc = "Get enumerated values variant"]
103    #[inline(always)]
104    pub const fn variant(&self) -> PERIODIC_SCHEDULE_ENABLE_A {
105        match self.bits {
106            false => PERIODIC_SCHEDULE_ENABLE_A::DISABLE,
107            true => PERIODIC_SCHEDULE_ENABLE_A::ENABLE,
108        }
109    }
110    #[doc = "Do not process the Periodic Schedule"]
111    #[inline(always)]
112    pub fn is_disable(&self) -> bool {
113        *self == PERIODIC_SCHEDULE_ENABLE_A::DISABLE
114    }
115    #[doc = "Use the PERIODICLISTBASE register to access the Periodic Schedule"]
116    #[inline(always)]
117    pub fn is_enable(&self) -> bool {
118        *self == PERIODIC_SCHEDULE_ENABLE_A::ENABLE
119    }
120}
121#[doc = "Field `periodic_schedule_enable` writer - Periodic Schedule Enable\n\nThis bit controls whether the host controller skips processing the Periodic Schedule."]
122pub type PERIODIC_SCHEDULE_ENABLE_W<'a, REG> =
123    crate::BitWriter<'a, REG, PERIODIC_SCHEDULE_ENABLE_A>;
124impl<'a, REG> PERIODIC_SCHEDULE_ENABLE_W<'a, REG>
125where
126    REG: crate::Writable + crate::RegisterSpec,
127{
128    #[doc = "Do not process the Periodic Schedule"]
129    #[inline(always)]
130    pub fn disable(self) -> &'a mut crate::W<REG> {
131        self.variant(PERIODIC_SCHEDULE_ENABLE_A::DISABLE)
132    }
133    #[doc = "Use the PERIODICLISTBASE register to access the Periodic Schedule"]
134    #[inline(always)]
135    pub fn enable(self) -> &'a mut crate::W<REG> {
136        self.variant(PERIODIC_SCHEDULE_ENABLE_A::ENABLE)
137    }
138}
139#[doc = "Field `asynchronous_schedule_enable` reader - Asynchronous Schedule Enable\n\nThis bit controls whether the host controller skips processing the Asynchronous Schedule."]
140pub type ASYNCHRONOUS_SCHEDULE_ENABLE_R = crate::BitReader<ASYNCHRONOUS_SCHEDULE_ENABLE_A>;
141#[doc = "Asynchronous Schedule Enable\n\nThis bit controls whether the host controller skips processing the Asynchronous Schedule.\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum ASYNCHRONOUS_SCHEDULE_ENABLE_A {
144    #[doc = "0: Do not process the Asynchronous Schedule"]
145    DISABLE = 0,
146    #[doc = "1: Use the ASYNLISTADDR register to access the Asynchronous Schedule"]
147    ENABLE = 1,
148}
149impl From<ASYNCHRONOUS_SCHEDULE_ENABLE_A> for bool {
150    #[inline(always)]
151    fn from(variant: ASYNCHRONOUS_SCHEDULE_ENABLE_A) -> Self {
152        variant as u8 != 0
153    }
154}
155impl ASYNCHRONOUS_SCHEDULE_ENABLE_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub const fn variant(&self) -> ASYNCHRONOUS_SCHEDULE_ENABLE_A {
159        match self.bits {
160            false => ASYNCHRONOUS_SCHEDULE_ENABLE_A::DISABLE,
161            true => ASYNCHRONOUS_SCHEDULE_ENABLE_A::ENABLE,
162        }
163    }
164    #[doc = "Do not process the Asynchronous Schedule"]
165    #[inline(always)]
166    pub fn is_disable(&self) -> bool {
167        *self == ASYNCHRONOUS_SCHEDULE_ENABLE_A::DISABLE
168    }
169    #[doc = "Use the ASYNLISTADDR register to access the Asynchronous Schedule"]
170    #[inline(always)]
171    pub fn is_enable(&self) -> bool {
172        *self == ASYNCHRONOUS_SCHEDULE_ENABLE_A::ENABLE
173    }
174}
175#[doc = "Field `asynchronous_schedule_enable` writer - Asynchronous Schedule Enable\n\nThis bit controls whether the host controller skips processing the Asynchronous Schedule."]
176pub type ASYNCHRONOUS_SCHEDULE_ENABLE_W<'a, REG> =
177    crate::BitWriter<'a, REG, ASYNCHRONOUS_SCHEDULE_ENABLE_A>;
178impl<'a, REG> ASYNCHRONOUS_SCHEDULE_ENABLE_W<'a, REG>
179where
180    REG: crate::Writable + crate::RegisterSpec,
181{
182    #[doc = "Do not process the Asynchronous Schedule"]
183    #[inline(always)]
184    pub fn disable(self) -> &'a mut crate::W<REG> {
185        self.variant(ASYNCHRONOUS_SCHEDULE_ENABLE_A::DISABLE)
186    }
187    #[doc = "Use the ASYNLISTADDR register to access the Asynchronous Schedule"]
188    #[inline(always)]
189    pub fn enable(self) -> &'a mut crate::W<REG> {
190        self.variant(ASYNCHRONOUS_SCHEDULE_ENABLE_A::ENABLE)
191    }
192}
193#[doc = "Field `interrupt_on_async_advance_doorbell` reader - Interrupt on Async Advance Doorbell\n\nThis bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USBSTS. if the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.\n\nThe host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one.\n\nSoftware should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results."]
194pub type INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL_R = crate::BitReader;
195#[doc = "Field `interrupt_on_async_advance_doorbell` writer - Interrupt on Async Advance Doorbell\n\nThis bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USBSTS. if the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.\n\nThe host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one.\n\nSoftware should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results."]
196pub type INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL_W<'a, REG> = crate::BitWriter<'a, REG>;
197#[doc = "Field `light_host_controller_reset` reader - Light Host Controller Reset (OPTIONAL)\n\nThis control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero (retaining port ownership relationships). A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it si safe for software to re- initialize the host controller. A host software read of this bit as a one indicates the Light Host"]
198pub type LIGHT_HOST_CONTROLLER_RESET_R = crate::BitReader;
199#[doc = "Field `light_host_controller_reset` writer - Light Host Controller Reset (OPTIONAL)\n\nThis control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero (retaining port ownership relationships). A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it si safe for software to re- initialize the host controller. A host software read of this bit as a one indicates the Light Host"]
200pub type LIGHT_HOST_CONTROLLER_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
201#[doc = "Field `asynchronous_schedule_park_mode_count` reader - Asynchronous Schedule Park Mode Count (OPTIONAL)\n\nAsynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 0x3 and is W/R. Otherwise it defaults to zero and is R. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid value are 0x1 to 0x3.Software must not write a zero to this bit when Park Mode Enable is a one as it will result in undefined behavior."]
202pub type ASYNCHRONOUS_SCHEDULE_PARK_MODE_COUNT_R = crate::FieldReader;
203#[doc = "Field `asynchronous_schedule_park_mode_enable` reader - Asynchronous Schedule Park Mode Enable (OPTIONAL)\n\nIf the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1 and is R/W. Otherwise the bit must be a zero and is Read Only. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is zero, Park mode is disabled."]
204pub type ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLE_R = crate::BitReader;
205#[doc = "Field `interrupt_threshold_control` reader - Interrupt Threshold Control\n\nThe value in this field is used by system software to select the maximum rate at which the host controller will issue interrupts."]
206pub type INTERRUPT_THRESHOLD_CONTROL_R = crate::FieldReader<INTERRUPT_THRESHOLD_CONTROL_A>;
207#[doc = "Interrupt Threshold Control\n\nThe value in this field is used by system software to select the maximum rate at which the host controller will issue interrupts.\n\nValue on reset: 0"]
208#[derive(Clone, Copy, Debug, PartialEq, Eq)]
209#[repr(u8)]
210pub enum INTERRUPT_THRESHOLD_CONTROL_A {
211    #[doc = "1: 1 micro-frame"]
212    MF1 = 1,
213    #[doc = "2: 2 micro-frames"]
214    MF2 = 2,
215    #[doc = "4: 4 micro-frames"]
216    MF4 = 4,
217    #[doc = "8: 8 micro-frames (default, equates to 1ms)"]
218    MF8 = 8,
219    #[doc = "16: 16 micro-frames (2ms)"]
220    MF16 = 16,
221    #[doc = "32: 32 micro-frames (4ms)"]
222    MF32 = 32,
223    #[doc = "64: 64 micro-frames (8ms)"]
224    MF64 = 64,
225}
226impl From<INTERRUPT_THRESHOLD_CONTROL_A> for u8 {
227    #[inline(always)]
228    fn from(variant: INTERRUPT_THRESHOLD_CONTROL_A) -> Self {
229        variant as _
230    }
231}
232impl crate::FieldSpec for INTERRUPT_THRESHOLD_CONTROL_A {
233    type Ux = u8;
234}
235impl INTERRUPT_THRESHOLD_CONTROL_R {
236    #[doc = "Get enumerated values variant"]
237    #[inline(always)]
238    pub const fn variant(&self) -> Option<INTERRUPT_THRESHOLD_CONTROL_A> {
239        match self.bits {
240            1 => Some(INTERRUPT_THRESHOLD_CONTROL_A::MF1),
241            2 => Some(INTERRUPT_THRESHOLD_CONTROL_A::MF2),
242            4 => Some(INTERRUPT_THRESHOLD_CONTROL_A::MF4),
243            8 => Some(INTERRUPT_THRESHOLD_CONTROL_A::MF8),
244            16 => Some(INTERRUPT_THRESHOLD_CONTROL_A::MF16),
245            32 => Some(INTERRUPT_THRESHOLD_CONTROL_A::MF32),
246            64 => Some(INTERRUPT_THRESHOLD_CONTROL_A::MF64),
247            _ => None,
248        }
249    }
250    #[doc = "1 micro-frame"]
251    #[inline(always)]
252    pub fn is_mf1(&self) -> bool {
253        *self == INTERRUPT_THRESHOLD_CONTROL_A::MF1
254    }
255    #[doc = "2 micro-frames"]
256    #[inline(always)]
257    pub fn is_mf2(&self) -> bool {
258        *self == INTERRUPT_THRESHOLD_CONTROL_A::MF2
259    }
260    #[doc = "4 micro-frames"]
261    #[inline(always)]
262    pub fn is_mf4(&self) -> bool {
263        *self == INTERRUPT_THRESHOLD_CONTROL_A::MF4
264    }
265    #[doc = "8 micro-frames (default, equates to 1ms)"]
266    #[inline(always)]
267    pub fn is_mf8(&self) -> bool {
268        *self == INTERRUPT_THRESHOLD_CONTROL_A::MF8
269    }
270    #[doc = "16 micro-frames (2ms)"]
271    #[inline(always)]
272    pub fn is_mf16(&self) -> bool {
273        *self == INTERRUPT_THRESHOLD_CONTROL_A::MF16
274    }
275    #[doc = "32 micro-frames (4ms)"]
276    #[inline(always)]
277    pub fn is_mf32(&self) -> bool {
278        *self == INTERRUPT_THRESHOLD_CONTROL_A::MF32
279    }
280    #[doc = "64 micro-frames (8ms)"]
281    #[inline(always)]
282    pub fn is_mf64(&self) -> bool {
283        *self == INTERRUPT_THRESHOLD_CONTROL_A::MF64
284    }
285}
286#[doc = "Field `interrupt_threshold_control` writer - Interrupt Threshold Control\n\nThe value in this field is used by system software to select the maximum rate at which the host controller will issue interrupts."]
287pub type INTERRUPT_THRESHOLD_CONTROL_W<'a, REG> =
288    crate::FieldWriter<'a, REG, 8, INTERRUPT_THRESHOLD_CONTROL_A>;
289impl<'a, REG> INTERRUPT_THRESHOLD_CONTROL_W<'a, REG>
290where
291    REG: crate::Writable + crate::RegisterSpec,
292    REG::Ux: From<u8>,
293{
294    #[doc = "1 micro-frame"]
295    #[inline(always)]
296    pub fn mf1(self) -> &'a mut crate::W<REG> {
297        self.variant(INTERRUPT_THRESHOLD_CONTROL_A::MF1)
298    }
299    #[doc = "2 micro-frames"]
300    #[inline(always)]
301    pub fn mf2(self) -> &'a mut crate::W<REG> {
302        self.variant(INTERRUPT_THRESHOLD_CONTROL_A::MF2)
303    }
304    #[doc = "4 micro-frames"]
305    #[inline(always)]
306    pub fn mf4(self) -> &'a mut crate::W<REG> {
307        self.variant(INTERRUPT_THRESHOLD_CONTROL_A::MF4)
308    }
309    #[doc = "8 micro-frames (default, equates to 1ms)"]
310    #[inline(always)]
311    pub fn mf8(self) -> &'a mut crate::W<REG> {
312        self.variant(INTERRUPT_THRESHOLD_CONTROL_A::MF8)
313    }
314    #[doc = "16 micro-frames (2ms)"]
315    #[inline(always)]
316    pub fn mf16(self) -> &'a mut crate::W<REG> {
317        self.variant(INTERRUPT_THRESHOLD_CONTROL_A::MF16)
318    }
319    #[doc = "32 micro-frames (4ms)"]
320    #[inline(always)]
321    pub fn mf32(self) -> &'a mut crate::W<REG> {
322        self.variant(INTERRUPT_THRESHOLD_CONTROL_A::MF32)
323    }
324    #[doc = "64 micro-frames (8ms)"]
325    #[inline(always)]
326    pub fn mf64(self) -> &'a mut crate::W<REG> {
327        self.variant(INTERRUPT_THRESHOLD_CONTROL_A::MF64)
328    }
329}
330impl R {
331    #[doc = "Bit 0 - Run/Stop\n\nWhen set to a 1, the Host Controller proceeds with execution of the schedule. When set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears this bit. The HC Halted bit indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state.\n\nSoftware must not write a one to this field unless the Host Controller is in the Halt State. The default value is 0x0."]
332    #[inline(always)]
333    pub fn run_stop(&self) -> RUN_STOP_R {
334        RUN_STOP_R::new((self.bits & 1) != 0)
335    }
336    #[doc = "Bit 1 - Host Controller Reset\n\nThis control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset.\n\nWhen software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports.\n\nAll operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s). Software must reinitialize the host controller as described in Section 4.1 of the CHEI Specification in order to return the host controller to an operational state. This bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.\n\nSoftware should not set this bit to a one when the HC Halted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
337    #[inline(always)]
338    pub fn host_controller_reset(&self) -> HOST_CONTROLLER_RESET_R {
339        HOST_CONTROLLER_RESET_R::new(((self.bits >> 1) & 1) != 0)
340    }
341    #[doc = "Bits 2:3 - This field is R/W only if Programmable Frame List Flag in the HCCPARAMS register is set to one. This field specifies the size of the Frame list."]
342    #[inline(always)]
343    pub fn frame_list_size(&self) -> FRAME_LIST_SIZE_R {
344        FRAME_LIST_SIZE_R::new(((self.bits >> 2) & 3) as u8)
345    }
346    #[doc = "Bit 4 - Periodic Schedule Enable\n\nThis bit controls whether the host controller skips processing the Periodic Schedule."]
347    #[inline(always)]
348    pub fn periodic_schedule_enable(&self) -> PERIODIC_SCHEDULE_ENABLE_R {
349        PERIODIC_SCHEDULE_ENABLE_R::new(((self.bits >> 4) & 1) != 0)
350    }
351    #[doc = "Bit 5 - Asynchronous Schedule Enable\n\nThis bit controls whether the host controller skips processing the Asynchronous Schedule."]
352    #[inline(always)]
353    pub fn asynchronous_schedule_enable(&self) -> ASYNCHRONOUS_SCHEDULE_ENABLE_R {
354        ASYNCHRONOUS_SCHEDULE_ENABLE_R::new(((self.bits >> 5) & 1) != 0)
355    }
356    #[doc = "Bit 6 - Interrupt on Async Advance Doorbell\n\nThis bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USBSTS. if the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.\n\nThe host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one.\n\nSoftware should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results."]
357    #[inline(always)]
358    pub fn interrupt_on_async_advance_doorbell(&self) -> INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL_R {
359        INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL_R::new(((self.bits >> 6) & 1) != 0)
360    }
361    #[doc = "Bit 7 - Light Host Controller Reset (OPTIONAL)\n\nThis control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero (retaining port ownership relationships). A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it si safe for software to re- initialize the host controller. A host software read of this bit as a one indicates the Light Host"]
362    #[inline(always)]
363    pub fn light_host_controller_reset(&self) -> LIGHT_HOST_CONTROLLER_RESET_R {
364        LIGHT_HOST_CONTROLLER_RESET_R::new(((self.bits >> 7) & 1) != 0)
365    }
366    #[doc = "Bits 8:9 - Asynchronous Schedule Park Mode Count (OPTIONAL)\n\nAsynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 0x3 and is W/R. Otherwise it defaults to zero and is R. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid value are 0x1 to 0x3.Software must not write a zero to this bit when Park Mode Enable is a one as it will result in undefined behavior."]
367    #[inline(always)]
368    pub fn asynchronous_schedule_park_mode_count(&self) -> ASYNCHRONOUS_SCHEDULE_PARK_MODE_COUNT_R {
369        ASYNCHRONOUS_SCHEDULE_PARK_MODE_COUNT_R::new(((self.bits >> 8) & 3) as u8)
370    }
371    #[doc = "Bit 11 - Asynchronous Schedule Park Mode Enable (OPTIONAL)\n\nIf the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1 and is R/W. Otherwise the bit must be a zero and is Read Only. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is zero, Park mode is disabled."]
372    #[inline(always)]
373    pub fn asynchronous_schedule_park_mode_enable(
374        &self,
375    ) -> ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLE_R {
376        ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLE_R::new(((self.bits >> 11) & 1) != 0)
377    }
378    #[doc = "Bits 16:23 - Interrupt Threshold Control\n\nThe value in this field is used by system software to select the maximum rate at which the host controller will issue interrupts."]
379    #[inline(always)]
380    pub fn interrupt_threshold_control(&self) -> INTERRUPT_THRESHOLD_CONTROL_R {
381        INTERRUPT_THRESHOLD_CONTROL_R::new(((self.bits >> 16) & 0xff) as u8)
382    }
383}
384impl W {
385    #[doc = "Bit 0 - Run/Stop\n\nWhen set to a 1, the Host Controller proceeds with execution of the schedule. When set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears this bit. The HC Halted bit indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state.\n\nSoftware must not write a one to this field unless the Host Controller is in the Halt State. The default value is 0x0."]
386    #[inline(always)]
387    #[must_use]
388    pub fn run_stop(&mut self) -> RUN_STOP_W<USBCMD_SPEC> {
389        RUN_STOP_W::new(self, 0)
390    }
391    #[doc = "Bit 1 - Host Controller Reset\n\nThis control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset.\n\nWhen software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports.\n\nAll operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s). Software must reinitialize the host controller as described in Section 4.1 of the CHEI Specification in order to return the host controller to an operational state. This bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.\n\nSoftware should not set this bit to a one when the HC Halted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
392    #[inline(always)]
393    #[must_use]
394    pub fn host_controller_reset(&mut self) -> HOST_CONTROLLER_RESET_W<USBCMD_SPEC> {
395        HOST_CONTROLLER_RESET_W::new(self, 1)
396    }
397    #[doc = "Bits 2:3 - This field is R/W only if Programmable Frame List Flag in the HCCPARAMS register is set to one. This field specifies the size of the Frame list."]
398    #[inline(always)]
399    #[must_use]
400    pub fn frame_list_size(&mut self) -> FRAME_LIST_SIZE_W<USBCMD_SPEC> {
401        FRAME_LIST_SIZE_W::new(self, 2)
402    }
403    #[doc = "Bit 4 - Periodic Schedule Enable\n\nThis bit controls whether the host controller skips processing the Periodic Schedule."]
404    #[inline(always)]
405    #[must_use]
406    pub fn periodic_schedule_enable(&mut self) -> PERIODIC_SCHEDULE_ENABLE_W<USBCMD_SPEC> {
407        PERIODIC_SCHEDULE_ENABLE_W::new(self, 4)
408    }
409    #[doc = "Bit 5 - Asynchronous Schedule Enable\n\nThis bit controls whether the host controller skips processing the Asynchronous Schedule."]
410    #[inline(always)]
411    #[must_use]
412    pub fn asynchronous_schedule_enable(&mut self) -> ASYNCHRONOUS_SCHEDULE_ENABLE_W<USBCMD_SPEC> {
413        ASYNCHRONOUS_SCHEDULE_ENABLE_W::new(self, 5)
414    }
415    #[doc = "Bit 6 - Interrupt on Async Advance Doorbell\n\nThis bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USBSTS. if the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.\n\nThe host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one.\n\nSoftware should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results."]
416    #[inline(always)]
417    #[must_use]
418    pub fn interrupt_on_async_advance_doorbell(
419        &mut self,
420    ) -> INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL_W<USBCMD_SPEC> {
421        INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL_W::new(self, 6)
422    }
423    #[doc = "Bit 7 - Light Host Controller Reset (OPTIONAL)\n\nThis control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero (retaining port ownership relationships). A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it si safe for software to re- initialize the host controller. A host software read of this bit as a one indicates the Light Host"]
424    #[inline(always)]
425    #[must_use]
426    pub fn light_host_controller_reset(&mut self) -> LIGHT_HOST_CONTROLLER_RESET_W<USBCMD_SPEC> {
427        LIGHT_HOST_CONTROLLER_RESET_W::new(self, 7)
428    }
429    #[doc = "Bits 16:23 - Interrupt Threshold Control\n\nThe value in this field is used by system software to select the maximum rate at which the host controller will issue interrupts."]
430    #[inline(always)]
431    #[must_use]
432    pub fn interrupt_threshold_control(&mut self) -> INTERRUPT_THRESHOLD_CONTROL_W<USBCMD_SPEC> {
433        INTERRUPT_THRESHOLD_CONTROL_W::new(self, 16)
434    }
435    #[doc = r" Writes raw bits to the register."]
436    #[doc = r""]
437    #[doc = r" # Safety"]
438    #[doc = r""]
439    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
440    #[inline(always)]
441    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
442        self.bits = bits;
443        self
444    }
445}
446#[doc = "EHCI USB Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbcmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbcmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
447pub struct USBCMD_SPEC;
448impl crate::RegisterSpec for USBCMD_SPEC {
449    type Ux = u32;
450}
451#[doc = "`read()` method returns [`usbcmd::R`](R) reader structure"]
452impl crate::Readable for USBCMD_SPEC {}
453#[doc = "`write(|w| ..)` method takes [`usbcmd::W`](W) writer structure"]
454impl crate::Writable for USBCMD_SPEC {
455    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
456    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
457}
458#[doc = "`reset()` method sets usbcmd to value 0"]
459impl crate::Resettable for USBCMD_SPEC {
460    const RESET_VALUE: Self::Ux = 0;
461}
d1_pac/usb1/ehci_operational/usbcmd.rs

d1_pac/usb1/ehci_operational/
usbcmd.rs
