1#[doc = "Register `portsc` reader"]
2pub type R = crate::R<PORTSC_SPEC>;
3#[doc = "Register `portsc` writer"]
4pub type W = crate::W<PORTSC_SPEC>;
5#[doc = "Field `current_connect_status` reader - Current Connect Status\n\nDevice is present on port when the value of this field is a one, and no device is present on port when the value of this field is a zero. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change(Bit 1) to be set.\n\nThis field is zero if Port Power zero."]
6pub type CURRENT_CONNECT_STATUS_R = crate::BitReader;
7#[doc = "Field `connect_status_change` reader - Connect Status Change\n\n1=Change in Current Connect Status\n\n0=No change\n\nIndicates a change has occurred in the current connect status of the port. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit. Software sets this bit to 0 by writing a 1 to it.\n\nThis field is zero if Port Power is zero."]
8pub type CONNECT_STATUS_CHANGE_R = crate::BitReader;
9#[doc = "Field `connect_status_change` writer - Connect Status Change\n\n1=Change in Current Connect Status\n\n0=No change\n\nIndicates a change has occurred in the current connect status of the port. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit. Software sets this bit to 0 by writing a 1 to it.\n\nThis field is zero if Port Power is zero."]
10pub type CONNECT_STATUS_CHANGE_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `port_enabled_disabled` reader - Port Enabled/Disabled\n\n1=Enable\n\n0=Disable\n\nPorts can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high- speed device.\n\nPorts can be disabled by either a fault condition(disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.\n\nWhen the port is disabled, downstream propagation of data is blocked on this port except for reset.\n\nThe default value of this field is '0'.\n\nThis field is zero if Port Power is zero."]
12pub type PORT_ENABLED_DISABLED_R = crate::BitReader;
13#[doc = "Field `port_enabled_disabled` writer - Port Enabled/Disabled\n\n1=Enable\n\n0=Disable\n\nPorts can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high- speed device.\n\nPorts can be disabled by either a fault condition(disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.\n\nWhen the port is disabled, downstream propagation of data is blocked on this port except for reset.\n\nThe default value of this field is '0'.\n\nThis field is zero if Port Power is zero."]
14pub type PORT_ENABLED_DISABLED_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `port_enable_disable_change` reader - Port Enable/Disable Change\n\n1 = Port enabled/disabled status has changed\n\n0 = No change\n\nFor the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by writing a 1 to it.\n\nThis field is zero if Port Power is zero."]
16pub type PORT_ENABLE_DISABLE_CHANGE_R = crate::BitReader;
17#[doc = "Field `port_enable_disable_change` writer - Port Enable/Disable Change\n\n1 = Port enabled/disabled status has changed\n\n0 = No change\n\nFor the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by writing a 1 to it.\n\nThis field is zero if Port Power is zero."]
18pub type PORT_ENABLE_DISABLE_CHANGE_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `over_current_active` reader - Over-current Active\n\n0 = This port does not have an over-current condition \n\n1 = This port currently has an over-current condition\n\nThis bit will automatically transition from a one to a zero when the over current condition is removed.\n\nThe default value of this bit is '0'."]
20pub type OVER_CURRENT_ACTIVE_R = crate::BitReader;
21#[doc = "Field `over_current_change` reader - Over-current Change\n\nThis bit gets set to a one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position."]
22pub type OVER_CURRENT_CHANGE_R = crate::BitReader;
23#[doc = "Field `over_current_change` writer - Over-current Change\n\nThis bit gets set to a one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position."]
24pub type OVER_CURRENT_CHANGE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `force_port_resume` reader - Force Port Resume\n\n1 = Resume detected/driven on port. 0 = No resume (K-state) detected/driven on port. Default value = 0.\n\nThis functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is not suspend and software transitions this bit to a one, then the effects on the bus are undefined.\n\nSoftware sets this bit to 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detect bit.\n\nNote that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this remains a one. Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed. Writing a zero (from one) causes the port to return high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a one until the port has switched to high-speed idle. The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.\n\nThis field is zero if Port Power is zero."]
26pub type FORCE_PORT_RESUME_R = crate::BitReader;
27#[doc = "Field `force_port_resume` writer - Force Port Resume\n\n1 = Resume detected/driven on port. 0 = No resume (K-state) detected/driven on port. Default value = 0.\n\nThis functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is not suspend and software transitions this bit to a one, then the effects on the bus are undefined.\n\nSoftware sets this bit to 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detect bit.\n\nNote that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this remains a one. Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed. Writing a zero (from one) causes the port to return high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a one until the port has switched to high-speed idle. The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.\n\nThis field is zero if Port Power is zero."]
28pub type FORCE_PORT_RESUME_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `suspend` reader - Suspend\n\nPort Enabled Bit and Suspend bit of this register define the port states\n\nWhen in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Not that the bit status does not change until the port is suspend and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.\n\nA write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when:\n\n1. Software sets the Force Port Resume bit to a zero(from a one).\n2. Software sets the Port Reset bit to a one(from a zero).\n\nIf host software sets this bit to a one when the port is not enabled(i.e. Port enabled bit is a zero), the results are undefined.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
30pub type SUSPEND_R = crate::BitReader<SUSPEND_A>;
31#[doc = "Suspend\n\nPort Enabled Bit and Suspend bit of this register define the port states\n\nWhen in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Not that the bit status does not change until the port is suspend and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.\n\nA write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when:\n\n1. Software sets the Force Port Resume bit to a zero(from a one).\n2. Software sets the Port Reset bit to a one(from a zero).\n\nIf host software sets this bit to a one when the port is not enabled(i.e. Port enabled bit is a zero), the results are undefined.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'.\n\nValue on reset: 0"]
32#[derive(Clone, Copy, Debug, PartialEq, Eq)]
33pub enum SUSPEND_A {
34 #[doc = "0: Not suspend"]
35 NOT_SUSPEND = 0,
36 #[doc = "1: Suspend"]
37 SUSPEND = 1,
38}
39impl From<SUSPEND_A> for bool {
40 #[inline(always)]
41 fn from(variant: SUSPEND_A) -> Self {
42 variant as u8 != 0
43 }
44}
45impl SUSPEND_R {
46 #[doc = "Get enumerated values variant"]
47 #[inline(always)]
48 pub const fn variant(&self) -> SUSPEND_A {
49 match self.bits {
50 false => SUSPEND_A::NOT_SUSPEND,
51 true => SUSPEND_A::SUSPEND,
52 }
53 }
54 #[doc = "Not suspend"]
55 #[inline(always)]
56 pub fn is_not_suspend(&self) -> bool {
57 *self == SUSPEND_A::NOT_SUSPEND
58 }
59 #[doc = "Suspend"]
60 #[inline(always)]
61 pub fn is_suspend(&self) -> bool {
62 *self == SUSPEND_A::SUSPEND
63 }
64}
65#[doc = "Field `suspend` writer - Suspend\n\nPort Enabled Bit and Suspend bit of this register define the port states\n\nWhen in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Not that the bit status does not change until the port is suspend and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.\n\nA write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when:\n\n1. Software sets the Force Port Resume bit to a zero(from a one).\n2. Software sets the Port Reset bit to a one(from a zero).\n\nIf host software sets this bit to a one when the port is not enabled(i.e. Port enabled bit is a zero), the results are undefined.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
66pub type SUSPEND_W<'a, REG> = crate::BitWriter<'a, REG, SUSPEND_A>;
67impl<'a, REG> SUSPEND_W<'a, REG>
68where
69 REG: crate::Writable + crate::RegisterSpec,
70{
71 #[doc = "Not suspend"]
72 #[inline(always)]
73 pub fn not_suspend(self) -> &'a mut crate::W<REG> {
74 self.variant(SUSPEND_A::NOT_SUSPEND)
75 }
76 #[doc = "Suspend"]
77 #[inline(always)]
78 pub fn suspend(self) -> &'a mut crate::W<REG> {
79 self.variant(SUSPEND_A::SUSPEND)
80 }
81}
82#[doc = "Field `port_reset` reader - Port Reset\n\n1=Port is in Reset. 0=Port is not in Reset. Default value = 0.\n\nWhen software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate the bus reset sequence. Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes.\n\n**Note: When software writes this bit to a one, it must also write a zero to the Port Enable bit.**\n\nNote that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. The bit status will not read as a zero until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state with 2ms of software writing this bit to a zero. The HC Halted bit in the USBSTS register should be a zero before software attempts to use this bit. The host controller may hold Port Reset asserted to a one when the HC Halted bit is a one. This field is zero if Port Power is zero."]
83pub type PORT_RESET_R = crate::BitReader;
84#[doc = "Field `port_reset` writer - Port Reset\n\n1=Port is in Reset. 0=Port is not in Reset. Default value = 0.\n\nWhen software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate the bus reset sequence. Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes.\n\n**Note: When software writes this bit to a one, it must also write a zero to the Port Enable bit.**\n\nNote that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. The bit status will not read as a zero until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state with 2ms of software writing this bit to a zero. The HC Halted bit in the USBSTS register should be a zero before software attempts to use this bit. The host controller may hold Port Reset asserted to a one when the HC Halted bit is a one. This field is zero if Port Power is zero."]
85pub type PORT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
86#[doc = "Field `line_status` reader - Line Status\n\nThese bits relect the current logical levels of the D+ (bit11) and D- (bit10) signal lines. These bits are used for detection of low-speed USB devices prior to port reset and enable sequence. This read only field is valid only when the port enable bit is zero and the current connect status bit is set to a one."]
87pub type LINE_STATUS_R = crate::FieldReader<LINE_STATUS_A>;
88#[doc = "Line Status\n\nThese bits relect the current logical levels of the D+ (bit11) and D- (bit10) signal lines. These bits are used for detection of low-speed USB devices prior to port reset and enable sequence. This read only field is valid only when the port enable bit is zero and the current connect status bit is set to a one.\n\nValue on reset: 0"]
89#[derive(Clone, Copy, Debug, PartialEq, Eq)]
90#[repr(u8)]
91pub enum LINE_STATUS_A {
92 #[doc = "0: Not Low-speed device, perform EHCI reset."]
93 SE0 = 0,
94 #[doc = "2: Not Low-speed device, perform EHCI reset."]
95 J_STATE = 2,
96 #[doc = "1: Low-speed device, release ownership of port."]
97 K_STATE = 1,
98 #[doc = "3: Not Low-speed device, perform EHCI reset."]
99 UNDEFINED = 3,
100}
101impl From<LINE_STATUS_A> for u8 {
102 #[inline(always)]
103 fn from(variant: LINE_STATUS_A) -> Self {
104 variant as _
105 }
106}
107impl crate::FieldSpec for LINE_STATUS_A {
108 type Ux = u8;
109}
110impl LINE_STATUS_R {
111 #[doc = "Get enumerated values variant"]
112 #[inline(always)]
113 pub const fn variant(&self) -> LINE_STATUS_A {
114 match self.bits {
115 0 => LINE_STATUS_A::SE0,
116 2 => LINE_STATUS_A::J_STATE,
117 1 => LINE_STATUS_A::K_STATE,
118 3 => LINE_STATUS_A::UNDEFINED,
119 _ => unreachable!(),
120 }
121 }
122 #[doc = "Not Low-speed device, perform EHCI reset."]
123 #[inline(always)]
124 pub fn is_se0(&self) -> bool {
125 *self == LINE_STATUS_A::SE0
126 }
127 #[doc = "Not Low-speed device, perform EHCI reset."]
128 #[inline(always)]
129 pub fn is_j_state(&self) -> bool {
130 *self == LINE_STATUS_A::J_STATE
131 }
132 #[doc = "Low-speed device, release ownership of port."]
133 #[inline(always)]
134 pub fn is_k_state(&self) -> bool {
135 *self == LINE_STATUS_A::K_STATE
136 }
137 #[doc = "Not Low-speed device, perform EHCI reset."]
138 #[inline(always)]
139 pub fn is_undefined(&self) -> bool {
140 *self == LINE_STATUS_A::UNDEFINED
141 }
142}
143#[doc = "Field `port_owner` reader - Port Owner\n\nThis bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally goes to 1b whenever the Configured bit is zero. System software uses this field to release ownership of the port to selected host controller (in the event that the attached device is not a high-speed device).Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that a companion host controller owns and controls the port. Default Value = 1b."]
144pub type PORT_OWNER_R = crate::BitReader;
145#[doc = "Field `port_owner` writer - Port Owner\n\nThis bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally goes to 1b whenever the Configured bit is zero. System software uses this field to release ownership of the port to selected host controller (in the event that the attached device is not a high-speed device).Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that a companion host controller owns and controls the port. Default Value = 1b."]
146pub type PORT_OWNER_W<'a, REG> = crate::BitWriter<'a, REG>;
147#[doc = "Field `port_test_control` reader - Port Test Control\n\nThe value in this field specifies the test mode of the port."]
148pub type PORT_TEST_CONTROL_R = crate::FieldReader<PORT_TEST_CONTROL_A>;
149#[doc = "Port Test Control\n\nThe value in this field specifies the test mode of the port.\n\nValue on reset: 0"]
150#[derive(Clone, Copy, Debug, PartialEq, Eq)]
151#[repr(u8)]
152pub enum PORT_TEST_CONTROL_A {
153 #[doc = "0: The port is NOT operating in a test mode."]
154 NOT_OPERATING = 0,
155 #[doc = "1: Test J_STATE"]
156 TEST_J_STATE = 1,
157 #[doc = "2: Test K_STATE"]
158 TEST_K_STATE = 2,
159 #[doc = "3: Test SE0_NAK"]
160 TEST_SE0_NAK = 3,
161 #[doc = "4: Test Packet"]
162 TEST_PACKET = 4,
163 #[doc = "5: Test FORCE_ENABLE"]
164 TEST_FORCE_ENABLE = 5,
165}
166impl From<PORT_TEST_CONTROL_A> for u8 {
167 #[inline(always)]
168 fn from(variant: PORT_TEST_CONTROL_A) -> Self {
169 variant as _
170 }
171}
172impl crate::FieldSpec for PORT_TEST_CONTROL_A {
173 type Ux = u8;
174}
175impl PORT_TEST_CONTROL_R {
176 #[doc = "Get enumerated values variant"]
177 #[inline(always)]
178 pub const fn variant(&self) -> Option<PORT_TEST_CONTROL_A> {
179 match self.bits {
180 0 => Some(PORT_TEST_CONTROL_A::NOT_OPERATING),
181 1 => Some(PORT_TEST_CONTROL_A::TEST_J_STATE),
182 2 => Some(PORT_TEST_CONTROL_A::TEST_K_STATE),
183 3 => Some(PORT_TEST_CONTROL_A::TEST_SE0_NAK),
184 4 => Some(PORT_TEST_CONTROL_A::TEST_PACKET),
185 5 => Some(PORT_TEST_CONTROL_A::TEST_FORCE_ENABLE),
186 _ => None,
187 }
188 }
189 #[doc = "The port is NOT operating in a test mode."]
190 #[inline(always)]
191 pub fn is_not_operating(&self) -> bool {
192 *self == PORT_TEST_CONTROL_A::NOT_OPERATING
193 }
194 #[doc = "Test J_STATE"]
195 #[inline(always)]
196 pub fn is_test_j_state(&self) -> bool {
197 *self == PORT_TEST_CONTROL_A::TEST_J_STATE
198 }
199 #[doc = "Test K_STATE"]
200 #[inline(always)]
201 pub fn is_test_k_state(&self) -> bool {
202 *self == PORT_TEST_CONTROL_A::TEST_K_STATE
203 }
204 #[doc = "Test SE0_NAK"]
205 #[inline(always)]
206 pub fn is_test_se0_nak(&self) -> bool {
207 *self == PORT_TEST_CONTROL_A::TEST_SE0_NAK
208 }
209 #[doc = "Test Packet"]
210 #[inline(always)]
211 pub fn is_test_packet(&self) -> bool {
212 *self == PORT_TEST_CONTROL_A::TEST_PACKET
213 }
214 #[doc = "Test FORCE_ENABLE"]
215 #[inline(always)]
216 pub fn is_test_force_enable(&self) -> bool {
217 *self == PORT_TEST_CONTROL_A::TEST_FORCE_ENABLE
218 }
219}
220#[doc = "Field `port_test_control` writer - Port Test Control\n\nThe value in this field specifies the test mode of the port."]
221pub type PORT_TEST_CONTROL_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PORT_TEST_CONTROL_A>;
222impl<'a, REG> PORT_TEST_CONTROL_W<'a, REG>
223where
224 REG: crate::Writable + crate::RegisterSpec,
225 REG::Ux: From<u8>,
226{
227 #[doc = "The port is NOT operating in a test mode."]
228 #[inline(always)]
229 pub fn not_operating(self) -> &'a mut crate::W<REG> {
230 self.variant(PORT_TEST_CONTROL_A::NOT_OPERATING)
231 }
232 #[doc = "Test J_STATE"]
233 #[inline(always)]
234 pub fn test_j_state(self) -> &'a mut crate::W<REG> {
235 self.variant(PORT_TEST_CONTROL_A::TEST_J_STATE)
236 }
237 #[doc = "Test K_STATE"]
238 #[inline(always)]
239 pub fn test_k_state(self) -> &'a mut crate::W<REG> {
240 self.variant(PORT_TEST_CONTROL_A::TEST_K_STATE)
241 }
242 #[doc = "Test SE0_NAK"]
243 #[inline(always)]
244 pub fn test_se0_nak(self) -> &'a mut crate::W<REG> {
245 self.variant(PORT_TEST_CONTROL_A::TEST_SE0_NAK)
246 }
247 #[doc = "Test Packet"]
248 #[inline(always)]
249 pub fn test_packet(self) -> &'a mut crate::W<REG> {
250 self.variant(PORT_TEST_CONTROL_A::TEST_PACKET)
251 }
252 #[doc = "Test FORCE_ENABLE"]
253 #[inline(always)]
254 pub fn test_force_enable(self) -> &'a mut crate::W<REG> {
255 self.variant(PORT_TEST_CONTROL_A::TEST_FORCE_ENABLE)
256 }
257}
258#[doc = "Field `wkcnnt_e` reader - Wake on Connect Enable (WKCNNT_E)\n\nWriting this bit to a one enable the port to be sensitive to device connects as wake-up events.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
259pub type WKCNNT_E_R = crate::BitReader;
260#[doc = "Field `wkcnnt_e` writer - Wake on Connect Enable (WKCNNT_E)\n\nWriting this bit to a one enable the port to be sensitive to device connects as wake-up events.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
261pub type WKCNNT_E_W<'a, REG> = crate::BitWriter<'a, REG>;
262#[doc = "Field `wkdscnnt_e` reader - Wake on Disconnect Enable (WKDSCNNT_E)\n\nWriting this bit to a one enables the port to be sensitive to device disconnects as wake-up events.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
263pub type WKDSCNNT_E_R = crate::BitReader;
264#[doc = "Field `wkdscnnt_e` writer - Wake on Disconnect Enable (WKDSCNNT_E)\n\nWriting this bit to a one enables the port to be sensitive to device disconnects as wake-up events.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
265pub type WKDSCNNT_E_W<'a, REG> = crate::BitWriter<'a, REG>;
266impl R {
267 #[doc = "Bit 0 - Current Connect Status\n\nDevice is present on port when the value of this field is a one, and no device is present on port when the value of this field is a zero. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change(Bit 1) to be set.\n\nThis field is zero if Port Power zero."]
268 #[inline(always)]
269 pub fn current_connect_status(&self) -> CURRENT_CONNECT_STATUS_R {
270 CURRENT_CONNECT_STATUS_R::new((self.bits & 1) != 0)
271 }
272 #[doc = "Bit 1 - Connect Status Change\n\n1=Change in Current Connect Status\n\n0=No change\n\nIndicates a change has occurred in the current connect status of the port. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit. Software sets this bit to 0 by writing a 1 to it.\n\nThis field is zero if Port Power is zero."]
273 #[inline(always)]
274 pub fn connect_status_change(&self) -> CONNECT_STATUS_CHANGE_R {
275 CONNECT_STATUS_CHANGE_R::new(((self.bits >> 1) & 1) != 0)
276 }
277 #[doc = "Bit 2 - Port Enabled/Disabled\n\n1=Enable\n\n0=Disable\n\nPorts can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high- speed device.\n\nPorts can be disabled by either a fault condition(disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.\n\nWhen the port is disabled, downstream propagation of data is blocked on this port except for reset.\n\nThe default value of this field is '0'.\n\nThis field is zero if Port Power is zero."]
278 #[inline(always)]
279 pub fn port_enabled_disabled(&self) -> PORT_ENABLED_DISABLED_R {
280 PORT_ENABLED_DISABLED_R::new(((self.bits >> 2) & 1) != 0)
281 }
282 #[doc = "Bit 3 - Port Enable/Disable Change\n\n1 = Port enabled/disabled status has changed\n\n0 = No change\n\nFor the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by writing a 1 to it.\n\nThis field is zero if Port Power is zero."]
283 #[inline(always)]
284 pub fn port_enable_disable_change(&self) -> PORT_ENABLE_DISABLE_CHANGE_R {
285 PORT_ENABLE_DISABLE_CHANGE_R::new(((self.bits >> 3) & 1) != 0)
286 }
287 #[doc = "Bit 4 - Over-current Active\n\n0 = This port does not have an over-current condition \n\n1 = This port currently has an over-current condition\n\nThis bit will automatically transition from a one to a zero when the over current condition is removed.\n\nThe default value of this bit is '0'."]
288 #[inline(always)]
289 pub fn over_current_active(&self) -> OVER_CURRENT_ACTIVE_R {
290 OVER_CURRENT_ACTIVE_R::new(((self.bits >> 4) & 1) != 0)
291 }
292 #[doc = "Bit 5 - Over-current Change\n\nThis bit gets set to a one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position."]
293 #[inline(always)]
294 pub fn over_current_change(&self) -> OVER_CURRENT_CHANGE_R {
295 OVER_CURRENT_CHANGE_R::new(((self.bits >> 5) & 1) != 0)
296 }
297 #[doc = "Bit 6 - Force Port Resume\n\n1 = Resume detected/driven on port. 0 = No resume (K-state) detected/driven on port. Default value = 0.\n\nThis functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is not suspend and software transitions this bit to a one, then the effects on the bus are undefined.\n\nSoftware sets this bit to 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detect bit.\n\nNote that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this remains a one. Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed. Writing a zero (from one) causes the port to return high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a one until the port has switched to high-speed idle. The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.\n\nThis field is zero if Port Power is zero."]
298 #[inline(always)]
299 pub fn force_port_resume(&self) -> FORCE_PORT_RESUME_R {
300 FORCE_PORT_RESUME_R::new(((self.bits >> 6) & 1) != 0)
301 }
302 #[doc = "Bit 7 - Suspend\n\nPort Enabled Bit and Suspend bit of this register define the port states\n\nWhen in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Not that the bit status does not change until the port is suspend and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.\n\nA write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when:\n\n1. Software sets the Force Port Resume bit to a zero(from a one).\n2. Software sets the Port Reset bit to a one(from a zero).\n\nIf host software sets this bit to a one when the port is not enabled(i.e. Port enabled bit is a zero), the results are undefined.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
303 #[inline(always)]
304 pub fn suspend(&self) -> SUSPEND_R {
305 SUSPEND_R::new(((self.bits >> 7) & 1) != 0)
306 }
307 #[doc = "Bit 8 - Port Reset\n\n1=Port is in Reset. 0=Port is not in Reset. Default value = 0.\n\nWhen software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate the bus reset sequence. Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes.\n\n**Note: When software writes this bit to a one, it must also write a zero to the Port Enable bit.**\n\nNote that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. The bit status will not read as a zero until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state with 2ms of software writing this bit to a zero. The HC Halted bit in the USBSTS register should be a zero before software attempts to use this bit. The host controller may hold Port Reset asserted to a one when the HC Halted bit is a one. This field is zero if Port Power is zero."]
308 #[inline(always)]
309 pub fn port_reset(&self) -> PORT_RESET_R {
310 PORT_RESET_R::new(((self.bits >> 8) & 1) != 0)
311 }
312 #[doc = "Bits 10:11 - Line Status\n\nThese bits relect the current logical levels of the D+ (bit11) and D- (bit10) signal lines. These bits are used for detection of low-speed USB devices prior to port reset and enable sequence. This read only field is valid only when the port enable bit is zero and the current connect status bit is set to a one."]
313 #[inline(always)]
314 pub fn line_status(&self) -> LINE_STATUS_R {
315 LINE_STATUS_R::new(((self.bits >> 10) & 3) as u8)
316 }
317 #[doc = "Bit 13 - Port Owner\n\nThis bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally goes to 1b whenever the Configured bit is zero. System software uses this field to release ownership of the port to selected host controller (in the event that the attached device is not a high-speed device).Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that a companion host controller owns and controls the port. Default Value = 1b."]
318 #[inline(always)]
319 pub fn port_owner(&self) -> PORT_OWNER_R {
320 PORT_OWNER_R::new(((self.bits >> 13) & 1) != 0)
321 }
322 #[doc = "Bits 16:19 - Port Test Control\n\nThe value in this field specifies the test mode of the port."]
323 #[inline(always)]
324 pub fn port_test_control(&self) -> PORT_TEST_CONTROL_R {
325 PORT_TEST_CONTROL_R::new(((self.bits >> 16) & 0x0f) as u8)
326 }
327 #[doc = "Bit 20 - Wake on Connect Enable (WKCNNT_E)\n\nWriting this bit to a one enable the port to be sensitive to device connects as wake-up events.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
328 #[inline(always)]
329 pub fn wkcnnt_e(&self) -> WKCNNT_E_R {
330 WKCNNT_E_R::new(((self.bits >> 20) & 1) != 0)
331 }
332 #[doc = "Bit 21 - Wake on Disconnect Enable (WKDSCNNT_E)\n\nWriting this bit to a one enables the port to be sensitive to device disconnects as wake-up events.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
333 #[inline(always)]
334 pub fn wkdscnnt_e(&self) -> WKDSCNNT_E_R {
335 WKDSCNNT_E_R::new(((self.bits >> 21) & 1) != 0)
336 }
337}
338impl W {
339 #[doc = "Bit 1 - Connect Status Change\n\n1=Change in Current Connect Status\n\n0=No change\n\nIndicates a change has occurred in the current connect status of the port. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit. Software sets this bit to 0 by writing a 1 to it.\n\nThis field is zero if Port Power is zero."]
340 #[inline(always)]
341 #[must_use]
342 pub fn connect_status_change(&mut self) -> CONNECT_STATUS_CHANGE_W<PORTSC_SPEC> {
343 CONNECT_STATUS_CHANGE_W::new(self, 1)
344 }
345 #[doc = "Bit 2 - Port Enabled/Disabled\n\n1=Enable\n\n0=Disable\n\nPorts can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high- speed device.\n\nPorts can be disabled by either a fault condition(disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.\n\nWhen the port is disabled, downstream propagation of data is blocked on this port except for reset.\n\nThe default value of this field is '0'.\n\nThis field is zero if Port Power is zero."]
346 #[inline(always)]
347 #[must_use]
348 pub fn port_enabled_disabled(&mut self) -> PORT_ENABLED_DISABLED_W<PORTSC_SPEC> {
349 PORT_ENABLED_DISABLED_W::new(self, 2)
350 }
351 #[doc = "Bit 3 - Port Enable/Disable Change\n\n1 = Port enabled/disabled status has changed\n\n0 = No change\n\nFor the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by writing a 1 to it.\n\nThis field is zero if Port Power is zero."]
352 #[inline(always)]
353 #[must_use]
354 pub fn port_enable_disable_change(&mut self) -> PORT_ENABLE_DISABLE_CHANGE_W<PORTSC_SPEC> {
355 PORT_ENABLE_DISABLE_CHANGE_W::new(self, 3)
356 }
357 #[doc = "Bit 5 - Over-current Change\n\nThis bit gets set to a one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position."]
358 #[inline(always)]
359 #[must_use]
360 pub fn over_current_change(&mut self) -> OVER_CURRENT_CHANGE_W<PORTSC_SPEC> {
361 OVER_CURRENT_CHANGE_W::new(self, 5)
362 }
363 #[doc = "Bit 6 - Force Port Resume\n\n1 = Resume detected/driven on port. 0 = No resume (K-state) detected/driven on port. Default value = 0.\n\nThis functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is not suspend and software transitions this bit to a one, then the effects on the bus are undefined.\n\nSoftware sets this bit to 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detect bit.\n\nNote that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this remains a one. Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed. Writing a zero (from one) causes the port to return high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a one until the port has switched to high-speed idle. The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.\n\nThis field is zero if Port Power is zero."]
364 #[inline(always)]
365 #[must_use]
366 pub fn force_port_resume(&mut self) -> FORCE_PORT_RESUME_W<PORTSC_SPEC> {
367 FORCE_PORT_RESUME_W::new(self, 6)
368 }
369 #[doc = "Bit 7 - Suspend\n\nPort Enabled Bit and Suspend bit of this register define the port states\n\nWhen in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Not that the bit status does not change until the port is suspend and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.\n\nA write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when:\n\n1. Software sets the Force Port Resume bit to a zero(from a one).\n2. Software sets the Port Reset bit to a one(from a zero).\n\nIf host software sets this bit to a one when the port is not enabled(i.e. Port enabled bit is a zero), the results are undefined.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
370 #[inline(always)]
371 #[must_use]
372 pub fn suspend(&mut self) -> SUSPEND_W<PORTSC_SPEC> {
373 SUSPEND_W::new(self, 7)
374 }
375 #[doc = "Bit 8 - Port Reset\n\n1=Port is in Reset. 0=Port is not in Reset. Default value = 0.\n\nWhen software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate the bus reset sequence. Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes.\n\n**Note: When software writes this bit to a one, it must also write a zero to the Port Enable bit.**\n\nNote that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. The bit status will not read as a zero until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state with 2ms of software writing this bit to a zero. The HC Halted bit in the USBSTS register should be a zero before software attempts to use this bit. The host controller may hold Port Reset asserted to a one when the HC Halted bit is a one. This field is zero if Port Power is zero."]
376 #[inline(always)]
377 #[must_use]
378 pub fn port_reset(&mut self) -> PORT_RESET_W<PORTSC_SPEC> {
379 PORT_RESET_W::new(self, 8)
380 }
381 #[doc = "Bit 13 - Port Owner\n\nThis bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally goes to 1b whenever the Configured bit is zero. System software uses this field to release ownership of the port to selected host controller (in the event that the attached device is not a high-speed device).Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that a companion host controller owns and controls the port. Default Value = 1b."]
382 #[inline(always)]
383 #[must_use]
384 pub fn port_owner(&mut self) -> PORT_OWNER_W<PORTSC_SPEC> {
385 PORT_OWNER_W::new(self, 13)
386 }
387 #[doc = "Bits 16:19 - Port Test Control\n\nThe value in this field specifies the test mode of the port."]
388 #[inline(always)]
389 #[must_use]
390 pub fn port_test_control(&mut self) -> PORT_TEST_CONTROL_W<PORTSC_SPEC> {
391 PORT_TEST_CONTROL_W::new(self, 16)
392 }
393 #[doc = "Bit 20 - Wake on Connect Enable (WKCNNT_E)\n\nWriting this bit to a one enable the port to be sensitive to device connects as wake-up events.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
394 #[inline(always)]
395 #[must_use]
396 pub fn wkcnnt_e(&mut self) -> WKCNNT_E_W<PORTSC_SPEC> {
397 WKCNNT_E_W::new(self, 20)
398 }
399 #[doc = "Bit 21 - Wake on Disconnect Enable (WKDSCNNT_E)\n\nWriting this bit to a one enables the port to be sensitive to device disconnects as wake-up events.\n\nThis field is zero if Port Power is zero.\n\nThe default value in this field is '0'."]
400 #[inline(always)]
401 #[must_use]
402 pub fn wkdscnnt_e(&mut self) -> WKDSCNNT_E_W<PORTSC_SPEC> {
403 WKDSCNNT_E_W::new(self, 21)
404 }
405 #[doc = r" Writes raw bits to the register."]
406 #[doc = r""]
407 #[doc = r" # Safety"]
408 #[doc = r""]
409 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
410 #[inline(always)]
411 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
412 self.bits = bits;
413 self
414 }
415}
416#[doc = "EHCI Port Status/Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`portsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`portsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
417pub struct PORTSC_SPEC;
418impl crate::RegisterSpec for PORTSC_SPEC {
419 type Ux = u32;
420}
421#[doc = "`read()` method returns [`portsc::R`](R) reader structure"]
422impl crate::Readable for PORTSC_SPEC {}
423#[doc = "`write(|w| ..)` method takes [`portsc::W`](W) writer structure"]
424impl crate::Writable for PORTSC_SPEC {
425 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
426 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
427}
428#[doc = "`reset()` method sets portsc to value 0x2000"]
429impl crate::Resettable for PORTSC_SPEC {
430 const RESET_VALUE: Self::Ux = 0x2000;
431}