d1_pac/uart/
rxdma_waddrl.rs

1#[doc = "Register `rxdma_waddrl` reader"]
2pub type R = crate::R<RXDMA_WADDRL_SPEC>;
3impl core::fmt::Debug for R {
4    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5        write!(f, "{}", self.bits())
6    }
7}
8impl core::fmt::Debug for crate::generic::Reg<RXDMA_WADDRL_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        core::fmt::Debug::fmt(&self.read(), f)
11    }
12}
13#[doc = "UART RXDMA Write Address Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_waddrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14pub struct RXDMA_WADDRL_SPEC;
15impl crate::RegisterSpec for RXDMA_WADDRL_SPEC {
16    type Ux = u32;
17}
18#[doc = "`read()` method returns [`rxdma_waddrl::R`](R) reader structure"]
19impl crate::Readable for RXDMA_WADDRL_SPEC {}
20#[doc = "`reset()` method sets rxdma_waddrl to value 0"]
21impl crate::Resettable for RXDMA_WADDRL_SPEC {
22    const RESET_VALUE: Self::Ux = 0;
23}
d1_pac/uart/rxdma_waddrl.rs

d1_pac/uart/
rxdma_waddrl.rs
