d1_pac/uart/
rxdma_sta.rs

1#[doc = "Register `rxdma_sta` reader"]
2pub type R = crate::R<RXDMA_STA_SPEC>;
3#[doc = "Register `rxdma_sta` writer"]
4pub type W = crate::W<RXDMA_STA_SPEC>;
5#[doc = "Field `busy` reader - "]
6pub type BUSY_R = crate::BitReader<BUSY_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum BUSY_A {
10    #[doc = "0: `0`"]
11    IDLE = 0,
12    #[doc = "1: `1`"]
13    BUSY = 1,
14}
15impl From<BUSY_A> for bool {
16    #[inline(always)]
17    fn from(variant: BUSY_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl BUSY_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> BUSY_A {
25        match self.bits {
26            false => BUSY_A::IDLE,
27            true => BUSY_A::BUSY,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_idle(&self) -> bool {
33        *self == BUSY_A::IDLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_busy(&self) -> bool {
38        *self == BUSY_A::BUSY
39    }
40}
41#[doc = "Field `busy` writer - "]
42pub type BUSY_W<'a, REG> = crate::BitWriter<'a, REG, BUSY_A>;
43impl<'a, REG> BUSY_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn idle(self) -> &'a mut crate::W<REG> {
50        self.variant(BUSY_A::IDLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn busy(self) -> &'a mut crate::W<REG> {
55        self.variant(BUSY_A::BUSY)
56    }
57}
58#[doc = "Field `buffer_read_address_updating` reader - "]
59pub type BUFFER_READ_ADDRESS_UPDATING_R = crate::BitReader<BUFFER_READ_ADDRESS_UPDATING_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum BUFFER_READ_ADDRESS_UPDATING_A {
63    #[doc = "0: `0`"]
64    READY = 0,
65    #[doc = "1: `1`"]
66    BUSY = 1,
67}
68impl From<BUFFER_READ_ADDRESS_UPDATING_A> for bool {
69    #[inline(always)]
70    fn from(variant: BUFFER_READ_ADDRESS_UPDATING_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl BUFFER_READ_ADDRESS_UPDATING_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> BUFFER_READ_ADDRESS_UPDATING_A {
78        match self.bits {
79            false => BUFFER_READ_ADDRESS_UPDATING_A::READY,
80            true => BUFFER_READ_ADDRESS_UPDATING_A::BUSY,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_ready(&self) -> bool {
86        *self == BUFFER_READ_ADDRESS_UPDATING_A::READY
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_busy(&self) -> bool {
91        *self == BUFFER_READ_ADDRESS_UPDATING_A::BUSY
92    }
93}
94#[doc = "Field `buffer_read_address_updating` writer - "]
95pub type BUFFER_READ_ADDRESS_UPDATING_W<'a, REG> =
96    crate::BitWriter<'a, REG, BUFFER_READ_ADDRESS_UPDATING_A>;
97impl<'a, REG> BUFFER_READ_ADDRESS_UPDATING_W<'a, REG>
98where
99    REG: crate::Writable + crate::RegisterSpec,
100{
101    #[doc = "`0`"]
102    #[inline(always)]
103    pub fn ready(self) -> &'a mut crate::W<REG> {
104        self.variant(BUFFER_READ_ADDRESS_UPDATING_A::READY)
105    }
106    #[doc = "`1`"]
107    #[inline(always)]
108    pub fn busy(self) -> &'a mut crate::W<REG> {
109        self.variant(BUFFER_READ_ADDRESS_UPDATING_A::BUSY)
110    }
111}
112impl R {
113    #[doc = "Bit 0"]
114    #[inline(always)]
115    pub fn busy(&self) -> BUSY_R {
116        BUSY_R::new((self.bits & 1) != 0)
117    }
118    #[doc = "Bit 1"]
119    #[inline(always)]
120    pub fn buffer_read_address_updating(&self) -> BUFFER_READ_ADDRESS_UPDATING_R {
121        BUFFER_READ_ADDRESS_UPDATING_R::new(((self.bits >> 1) & 1) != 0)
122    }
123}
124impl W {
125    #[doc = "Bit 0"]
126    #[inline(always)]
127    #[must_use]
128    pub fn busy(&mut self) -> BUSY_W<RXDMA_STA_SPEC> {
129        BUSY_W::new(self, 0)
130    }
131    #[doc = "Bit 1"]
132    #[inline(always)]
133    #[must_use]
134    pub fn buffer_read_address_updating(
135        &mut self,
136    ) -> BUFFER_READ_ADDRESS_UPDATING_W<RXDMA_STA_SPEC> {
137        BUFFER_READ_ADDRESS_UPDATING_W::new(self, 1)
138    }
139    #[doc = r" Writes raw bits to the register."]
140    #[doc = r""]
141    #[doc = r" # Safety"]
142    #[doc = r""]
143    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
144    #[inline(always)]
145    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
146        self.bits = bits;
147        self
148    }
149}
150#[doc = "UART RXDMA Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
151pub struct RXDMA_STA_SPEC;
152impl crate::RegisterSpec for RXDMA_STA_SPEC {
153    type Ux = u32;
154}
155#[doc = "`read()` method returns [`rxdma_sta::R`](R) reader structure"]
156impl crate::Readable for RXDMA_STA_SPEC {}
157#[doc = "`write(|w| ..)` method takes [`rxdma_sta::W`](W) writer structure"]
158impl crate::Writable for RXDMA_STA_SPEC {
159    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
160    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
161}
162#[doc = "`reset()` method sets rxdma_sta to value 0"]
163impl crate::Resettable for RXDMA_STA_SPEC {
164    const RESET_VALUE: Self::Ux = 0;
165}
d1_pac/uart/rxdma_sta.rs

d1_pac/uart/
rxdma_sta.rs
