d1_pac/uart/
rxdma_ie.rs

1#[doc = "Register `rxdma_ie` reader"]
2pub type R = crate::R<RXDMA_IE_SPEC>;
3#[doc = "Register `rxdma_ie` writer"]
4pub type W = crate::W<RXDMA_IE_SPEC>;
5#[doc = "Field `limit_done` reader - "]
6pub type LIMIT_DONE_R = crate::BitReader;
7#[doc = "Field `limit_done` writer - "]
8pub type LIMIT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `blk_done` reader - "]
10pub type BLK_DONE_R = crate::BitReader;
11#[doc = "Field `blk_done` writer - "]
12pub type BLK_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `timeout_done` reader - "]
14pub type TIMEOUT_DONE_R = crate::BitReader;
15#[doc = "Field `timeout_done` writer - "]
16pub type TIMEOUT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `buffer_overrun` reader - "]
18pub type BUFFER_OVERRUN_R = crate::BitReader;
19#[doc = "Field `buffer_overrun` writer - "]
20pub type BUFFER_OVERRUN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0"]
23    #[inline(always)]
24    pub fn limit_done(&self) -> LIMIT_DONE_R {
25        LIMIT_DONE_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1"]
28    #[inline(always)]
29    pub fn blk_done(&self) -> BLK_DONE_R {
30        BLK_DONE_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2"]
33    #[inline(always)]
34    pub fn timeout_done(&self) -> TIMEOUT_DONE_R {
35        TIMEOUT_DONE_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3"]
38    #[inline(always)]
39    pub fn buffer_overrun(&self) -> BUFFER_OVERRUN_R {
40        BUFFER_OVERRUN_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bit 0"]
45    #[inline(always)]
46    #[must_use]
47    pub fn limit_done(&mut self) -> LIMIT_DONE_W<RXDMA_IE_SPEC> {
48        LIMIT_DONE_W::new(self, 0)
49    }
50    #[doc = "Bit 1"]
51    #[inline(always)]
52    #[must_use]
53    pub fn blk_done(&mut self) -> BLK_DONE_W<RXDMA_IE_SPEC> {
54        BLK_DONE_W::new(self, 1)
55    }
56    #[doc = "Bit 2"]
57    #[inline(always)]
58    #[must_use]
59    pub fn timeout_done(&mut self) -> TIMEOUT_DONE_W<RXDMA_IE_SPEC> {
60        TIMEOUT_DONE_W::new(self, 2)
61    }
62    #[doc = "Bit 3"]
63    #[inline(always)]
64    #[must_use]
65    pub fn buffer_overrun(&mut self) -> BUFFER_OVERRUN_W<RXDMA_IE_SPEC> {
66        BUFFER_OVERRUN_W::new(self, 3)
67    }
68    #[doc = r" Writes raw bits to the register."]
69    #[doc = r""]
70    #[doc = r" # Safety"]
71    #[doc = r""]
72    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.bits = bits;
76        self
77    }
78}
79#[doc = "UART RXDMA Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_ie::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_ie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct RXDMA_IE_SPEC;
81impl crate::RegisterSpec for RXDMA_IE_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`rxdma_ie::R`](R) reader structure"]
85impl crate::Readable for RXDMA_IE_SPEC {}
86#[doc = "`write(|w| ..)` method takes [`rxdma_ie::W`](W) writer structure"]
87impl crate::Writable for RXDMA_IE_SPEC {
88    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
89    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
90}
91#[doc = "`reset()` method sets rxdma_ie to value 0"]
92impl crate::Resettable for RXDMA_IE_SPEC {
93    const RESET_VALUE: Self::Ux = 0;
94}
d1_pac/uart/rxdma_ie.rs

d1_pac/uart/
rxdma_ie.rs
