d1_pac/uart/
rxdma_ctrl.rs

1#[doc = "Register `rxdma_ctrl` reader"]
2pub type R = crate::R<RXDMA_CTRL_SPEC>;
3#[doc = "Register `rxdma_ctrl` writer"]
4pub type W = crate::W<RXDMA_CTRL_SPEC>;
5#[doc = "Field `enable` reader - "]
6pub type ENABLE_R = crate::BitReader<ENABLE_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum ENABLE_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<ENABLE_A> for bool {
16    #[inline(always)]
17    fn from(variant: ENABLE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl ENABLE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> ENABLE_A {
25        match self.bits {
26            false => ENABLE_A::DISABLE,
27            true => ENABLE_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == ENABLE_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == ENABLE_A::ENABLE
39    }
40}
41#[doc = "Field `enable` writer - "]
42pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, ENABLE_A>;
43impl<'a, REG> ENABLE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(ENABLE_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(ENABLE_A::ENABLE)
56    }
57}
58#[doc = "Field `mode` reader - "]
59pub type MODE_R = crate::BitReader<MODE_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum MODE_A {
63    #[doc = "0: `0`"]
64    CONTINOUS = 0,
65    #[doc = "1: `1`"]
66    LIMITED = 1,
67}
68impl From<MODE_A> for bool {
69    #[inline(always)]
70    fn from(variant: MODE_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl MODE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> MODE_A {
78        match self.bits {
79            false => MODE_A::CONTINOUS,
80            true => MODE_A::LIMITED,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_continous(&self) -> bool {
86        *self == MODE_A::CONTINOUS
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_limited(&self) -> bool {
91        *self == MODE_A::LIMITED
92    }
93}
94#[doc = "Field `mode` writer - "]
95pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG, MODE_A>;
96impl<'a, REG> MODE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn continous(self) -> &'a mut crate::W<REG> {
103        self.variant(MODE_A::CONTINOUS)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn limited(self) -> &'a mut crate::W<REG> {
108        self.variant(MODE_A::LIMITED)
109    }
110}
111#[doc = "Field `blk_size` reader - "]
112pub type BLK_SIZE_R = crate::FieldReader<BLK_SIZE_A>;
113#[doc = "\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115#[repr(u8)]
116pub enum BLK_SIZE_A {
117    #[doc = "0: `0`"]
118    B8 = 0,
119    #[doc = "1: `1`"]
120    B16 = 1,
121    #[doc = "2: `10`"]
122    B32 = 2,
123    #[doc = "3: `11`"]
124    B64 = 3,
125}
126impl From<BLK_SIZE_A> for u8 {
127    #[inline(always)]
128    fn from(variant: BLK_SIZE_A) -> Self {
129        variant as _
130    }
131}
132impl crate::FieldSpec for BLK_SIZE_A {
133    type Ux = u8;
134}
135impl BLK_SIZE_R {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub const fn variant(&self) -> BLK_SIZE_A {
139        match self.bits {
140            0 => BLK_SIZE_A::B8,
141            1 => BLK_SIZE_A::B16,
142            2 => BLK_SIZE_A::B32,
143            3 => BLK_SIZE_A::B64,
144            _ => unreachable!(),
145        }
146    }
147    #[doc = "`0`"]
148    #[inline(always)]
149    pub fn is_b8(&self) -> bool {
150        *self == BLK_SIZE_A::B8
151    }
152    #[doc = "`1`"]
153    #[inline(always)]
154    pub fn is_b16(&self) -> bool {
155        *self == BLK_SIZE_A::B16
156    }
157    #[doc = "`10`"]
158    #[inline(always)]
159    pub fn is_b32(&self) -> bool {
160        *self == BLK_SIZE_A::B32
161    }
162    #[doc = "`11`"]
163    #[inline(always)]
164    pub fn is_b64(&self) -> bool {
165        *self == BLK_SIZE_A::B64
166    }
167}
168#[doc = "Field `blk_size` writer - "]
169pub type BLK_SIZE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, BLK_SIZE_A>;
170impl<'a, REG> BLK_SIZE_W<'a, REG>
171where
172    REG: crate::Writable + crate::RegisterSpec,
173    REG::Ux: From<u8>,
174{
175    #[doc = "`0`"]
176    #[inline(always)]
177    pub fn b8(self) -> &'a mut crate::W<REG> {
178        self.variant(BLK_SIZE_A::B8)
179    }
180    #[doc = "`1`"]
181    #[inline(always)]
182    pub fn b16(self) -> &'a mut crate::W<REG> {
183        self.variant(BLK_SIZE_A::B16)
184    }
185    #[doc = "`10`"]
186    #[inline(always)]
187    pub fn b32(self) -> &'a mut crate::W<REG> {
188        self.variant(BLK_SIZE_A::B32)
189    }
190    #[doc = "`11`"]
191    #[inline(always)]
192    pub fn b64(self) -> &'a mut crate::W<REG> {
193        self.variant(BLK_SIZE_A::B64)
194    }
195}
196#[doc = "Field `ahb_burst_mode` reader - Set for AHB port burst supported"]
197pub type AHB_BURST_MODE_R = crate::FieldReader<AHB_BURST_MODE_A>;
198#[doc = "Set for AHB port burst supported\n\nValue on reset: 0"]
199#[derive(Clone, Copy, Debug, PartialEq, Eq)]
200#[repr(u8)]
201pub enum AHB_BURST_MODE_A {
202    #[doc = "0: `0`"]
203    SINGLE = 0,
204    #[doc = "1: `1`"]
205    INCR4 = 1,
206    #[doc = "2: `10`"]
207    INCR8 = 2,
208    #[doc = "3: `11`"]
209    INCR16 = 3,
210}
211impl From<AHB_BURST_MODE_A> for u8 {
212    #[inline(always)]
213    fn from(variant: AHB_BURST_MODE_A) -> Self {
214        variant as _
215    }
216}
217impl crate::FieldSpec for AHB_BURST_MODE_A {
218    type Ux = u8;
219}
220impl AHB_BURST_MODE_R {
221    #[doc = "Get enumerated values variant"]
222    #[inline(always)]
223    pub const fn variant(&self) -> AHB_BURST_MODE_A {
224        match self.bits {
225            0 => AHB_BURST_MODE_A::SINGLE,
226            1 => AHB_BURST_MODE_A::INCR4,
227            2 => AHB_BURST_MODE_A::INCR8,
228            3 => AHB_BURST_MODE_A::INCR16,
229            _ => unreachable!(),
230        }
231    }
232    #[doc = "`0`"]
233    #[inline(always)]
234    pub fn is_single(&self) -> bool {
235        *self == AHB_BURST_MODE_A::SINGLE
236    }
237    #[doc = "`1`"]
238    #[inline(always)]
239    pub fn is_incr4(&self) -> bool {
240        *self == AHB_BURST_MODE_A::INCR4
241    }
242    #[doc = "`10`"]
243    #[inline(always)]
244    pub fn is_incr8(&self) -> bool {
245        *self == AHB_BURST_MODE_A::INCR8
246    }
247    #[doc = "`11`"]
248    #[inline(always)]
249    pub fn is_incr16(&self) -> bool {
250        *self == AHB_BURST_MODE_A::INCR16
251    }
252}
253#[doc = "Field `ahb_burst_mode` writer - Set for AHB port burst supported"]
254pub type AHB_BURST_MODE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, AHB_BURST_MODE_A>;
255impl<'a, REG> AHB_BURST_MODE_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258    REG::Ux: From<u8>,
259{
260    #[doc = "`0`"]
261    #[inline(always)]
262    pub fn single(self) -> &'a mut crate::W<REG> {
263        self.variant(AHB_BURST_MODE_A::SINGLE)
264    }
265    #[doc = "`1`"]
266    #[inline(always)]
267    pub fn incr4(self) -> &'a mut crate::W<REG> {
268        self.variant(AHB_BURST_MODE_A::INCR4)
269    }
270    #[doc = "`10`"]
271    #[inline(always)]
272    pub fn incr8(self) -> &'a mut crate::W<REG> {
273        self.variant(AHB_BURST_MODE_A::INCR8)
274    }
275    #[doc = "`11`"]
276    #[inline(always)]
277    pub fn incr16(self) -> &'a mut crate::W<REG> {
278        self.variant(AHB_BURST_MODE_A::INCR16)
279    }
280}
281#[doc = "Field `timeout_enable` reader - RXDMA Timeout Enable"]
282pub type TIMEOUT_ENABLE_R = crate::BitReader;
283#[doc = "Field `timeout_enable` writer - RXDMA Timeout Enable"]
284pub type TIMEOUT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
285#[doc = "Field `timeout_threshold` reader - RXDMA Timeout Threshold\n\nUnit is 1 UART bit time"]
286pub type TIMEOUT_THRESHOLD_R = crate::FieldReader<u16>;
287#[doc = "Field `timeout_threshold` writer - RXDMA Timeout Threshold\n\nUnit is 1 UART bit time"]
288pub type TIMEOUT_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
289impl R {
290    #[doc = "Bit 0"]
291    #[inline(always)]
292    pub fn enable(&self) -> ENABLE_R {
293        ENABLE_R::new((self.bits & 1) != 0)
294    }
295    #[doc = "Bit 1"]
296    #[inline(always)]
297    pub fn mode(&self) -> MODE_R {
298        MODE_R::new(((self.bits >> 1) & 1) != 0)
299    }
300    #[doc = "Bits 2:3"]
301    #[inline(always)]
302    pub fn blk_size(&self) -> BLK_SIZE_R {
303        BLK_SIZE_R::new(((self.bits >> 2) & 3) as u8)
304    }
305    #[doc = "Bits 4:5 - Set for AHB port burst supported"]
306    #[inline(always)]
307    pub fn ahb_burst_mode(&self) -> AHB_BURST_MODE_R {
308        AHB_BURST_MODE_R::new(((self.bits >> 4) & 3) as u8)
309    }
310    #[doc = "Bit 6 - RXDMA Timeout Enable"]
311    #[inline(always)]
312    pub fn timeout_enable(&self) -> TIMEOUT_ENABLE_R {
313        TIMEOUT_ENABLE_R::new(((self.bits >> 6) & 1) != 0)
314    }
315    #[doc = "Bits 8:23 - RXDMA Timeout Threshold\n\nUnit is 1 UART bit time"]
316    #[inline(always)]
317    pub fn timeout_threshold(&self) -> TIMEOUT_THRESHOLD_R {
318        TIMEOUT_THRESHOLD_R::new(((self.bits >> 8) & 0xffff) as u16)
319    }
320}
321impl W {
322    #[doc = "Bit 0"]
323    #[inline(always)]
324    #[must_use]
325    pub fn enable(&mut self) -> ENABLE_W<RXDMA_CTRL_SPEC> {
326        ENABLE_W::new(self, 0)
327    }
328    #[doc = "Bit 1"]
329    #[inline(always)]
330    #[must_use]
331    pub fn mode(&mut self) -> MODE_W<RXDMA_CTRL_SPEC> {
332        MODE_W::new(self, 1)
333    }
334    #[doc = "Bits 2:3"]
335    #[inline(always)]
336    #[must_use]
337    pub fn blk_size(&mut self) -> BLK_SIZE_W<RXDMA_CTRL_SPEC> {
338        BLK_SIZE_W::new(self, 2)
339    }
340    #[doc = "Bits 4:5 - Set for AHB port burst supported"]
341    #[inline(always)]
342    #[must_use]
343    pub fn ahb_burst_mode(&mut self) -> AHB_BURST_MODE_W<RXDMA_CTRL_SPEC> {
344        AHB_BURST_MODE_W::new(self, 4)
345    }
346    #[doc = "Bit 6 - RXDMA Timeout Enable"]
347    #[inline(always)]
348    #[must_use]
349    pub fn timeout_enable(&mut self) -> TIMEOUT_ENABLE_W<RXDMA_CTRL_SPEC> {
350        TIMEOUT_ENABLE_W::new(self, 6)
351    }
352    #[doc = "Bits 8:23 - RXDMA Timeout Threshold\n\nUnit is 1 UART bit time"]
353    #[inline(always)]
354    #[must_use]
355    pub fn timeout_threshold(&mut self) -> TIMEOUT_THRESHOLD_W<RXDMA_CTRL_SPEC> {
356        TIMEOUT_THRESHOLD_W::new(self, 8)
357    }
358    #[doc = r" Writes raw bits to the register."]
359    #[doc = r""]
360    #[doc = r" # Safety"]
361    #[doc = r""]
362    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
363    #[inline(always)]
364    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
365        self.bits = bits;
366        self
367    }
368}
369#[doc = "UART RXDMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
370pub struct RXDMA_CTRL_SPEC;
371impl crate::RegisterSpec for RXDMA_CTRL_SPEC {
372    type Ux = u32;
373}
374#[doc = "`read()` method returns [`rxdma_ctrl::R`](R) reader structure"]
375impl crate::Readable for RXDMA_CTRL_SPEC {}
376#[doc = "`write(|w| ..)` method takes [`rxdma_ctrl::W`](W) writer structure"]
377impl crate::Writable for RXDMA_CTRL_SPEC {
378    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
379    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
380}
381#[doc = "`reset()` method sets rxdma_ctrl to value 0"]
382impl crate::Resettable for RXDMA_CTRL_SPEC {
383    const RESET_VALUE: Self::Ux = 0;
384}
d1_pac/uart/rxdma_ctrl.rs

d1_pac/uart/
rxdma_ctrl.rs
