d1_pac/uart/
ier.rs

1#[doc = "Register `ier` reader"]
2pub type R = crate::R<IER_SPEC>;
3#[doc = "Register `ier` writer"]
4pub type W = crate::W<IER_SPEC>;
5#[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt"]
6pub type ERBFI_R = crate::BitReader<ERBFI_A>;
7#[doc = "Enable Received Data Available Interrupt\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum ERBFI_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<ERBFI_A> for bool {
16    #[inline(always)]
17    fn from(variant: ERBFI_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl ERBFI_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> ERBFI_A {
25        match self.bits {
26            false => ERBFI_A::DISABLE,
27            true => ERBFI_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == ERBFI_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == ERBFI_A::ENABLE
39    }
40}
41#[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt"]
42pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG, ERBFI_A>;
43impl<'a, REG> ERBFI_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(ERBFI_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(ERBFI_A::ENABLE)
56    }
57}
58#[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt"]
59pub type ETBEI_R = crate::BitReader<ETBEI_A>;
60#[doc = "Enable Transmit Holding Register Empty Interrupt\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum ETBEI_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<ETBEI_A> for bool {
69    #[inline(always)]
70    fn from(variant: ETBEI_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl ETBEI_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> ETBEI_A {
78        match self.bits {
79            false => ETBEI_A::DISABLE,
80            true => ETBEI_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == ETBEI_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == ETBEI_A::ENABLE
92    }
93}
94#[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt"]
95pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG, ETBEI_A>;
96impl<'a, REG> ETBEI_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(ETBEI_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(ETBEI_A::ENABLE)
109    }
110}
111#[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt"]
112pub type ELSI_R = crate::BitReader<ELSI_A>;
113#[doc = "Enable Receiver Line Status Interrupt\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum ELSI_A {
116    #[doc = "0: `0`"]
117    DISABLE = 0,
118    #[doc = "1: `1`"]
119    ENABLE = 1,
120}
121impl From<ELSI_A> for bool {
122    #[inline(always)]
123    fn from(variant: ELSI_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl ELSI_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> ELSI_A {
131        match self.bits {
132            false => ELSI_A::DISABLE,
133            true => ELSI_A::ENABLE,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == ELSI_A::DISABLE
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == ELSI_A::ENABLE
145    }
146}
147#[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt"]
148pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG, ELSI_A>;
149impl<'a, REG> ELSI_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(ELSI_A::DISABLE)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(ELSI_A::ENABLE)
162    }
163}
164#[doc = "Field `edssi` reader - Enable Modem Status Interrupt"]
165pub type EDSSI_R = crate::BitReader<EDSSI_A>;
166#[doc = "Enable Modem Status Interrupt\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum EDSSI_A {
169    #[doc = "0: `0`"]
170    DISABLE = 0,
171    #[doc = "1: `1`"]
172    ENABLE = 1,
173}
174impl From<EDSSI_A> for bool {
175    #[inline(always)]
176    fn from(variant: EDSSI_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl EDSSI_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> EDSSI_A {
184        match self.bits {
185            false => EDSSI_A::DISABLE,
186            true => EDSSI_A::ENABLE,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_disable(&self) -> bool {
192        *self == EDSSI_A::DISABLE
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_enable(&self) -> bool {
197        *self == EDSSI_A::ENABLE
198    }
199}
200#[doc = "Field `edssi` writer - Enable Modem Status Interrupt"]
201pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG, EDSSI_A>;
202impl<'a, REG> EDSSI_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn disable(self) -> &'a mut crate::W<REG> {
209        self.variant(EDSSI_A::DISABLE)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn enable(self) -> &'a mut crate::W<REG> {
214        self.variant(EDSSI_A::ENABLE)
215    }
216}
217#[doc = "Field `rs485_int_en` reader - RS485 Interrupt Enable"]
218pub type RS485_INT_EN_R = crate::BitReader<RS485_INT_EN_A>;
219#[doc = "RS485 Interrupt Enable\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum RS485_INT_EN_A {
222    #[doc = "0: `0`"]
223    DISABLE = 0,
224    #[doc = "1: `1`"]
225    ENABLE = 1,
226}
227impl From<RS485_INT_EN_A> for bool {
228    #[inline(always)]
229    fn from(variant: RS485_INT_EN_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl RS485_INT_EN_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> RS485_INT_EN_A {
237        match self.bits {
238            false => RS485_INT_EN_A::DISABLE,
239            true => RS485_INT_EN_A::ENABLE,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_disable(&self) -> bool {
245        *self == RS485_INT_EN_A::DISABLE
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_enable(&self) -> bool {
250        *self == RS485_INT_EN_A::ENABLE
251    }
252}
253#[doc = "Field `rs485_int_en` writer - RS485 Interrupt Enable"]
254pub type RS485_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, RS485_INT_EN_A>;
255impl<'a, REG> RS485_INT_EN_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn disable(self) -> &'a mut crate::W<REG> {
262        self.variant(RS485_INT_EN_A::DISABLE)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn enable(self) -> &'a mut crate::W<REG> {
267        self.variant(RS485_INT_EN_A::ENABLE)
268    }
269}
270#[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable"]
271pub type PTIME_R = crate::BitReader<PTIME_A>;
272#[doc = "Programmable THRE Interrupt Mode Enable\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum PTIME_A {
275    #[doc = "0: `0`"]
276    DISABLE = 0,
277    #[doc = "1: `1`"]
278    ENABLE = 1,
279}
280impl From<PTIME_A> for bool {
281    #[inline(always)]
282    fn from(variant: PTIME_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl PTIME_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> PTIME_A {
290        match self.bits {
291            false => PTIME_A::DISABLE,
292            true => PTIME_A::ENABLE,
293        }
294    }
295    #[doc = "`0`"]
296    #[inline(always)]
297    pub fn is_disable(&self) -> bool {
298        *self == PTIME_A::DISABLE
299    }
300    #[doc = "`1`"]
301    #[inline(always)]
302    pub fn is_enable(&self) -> bool {
303        *self == PTIME_A::ENABLE
304    }
305}
306#[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable"]
307pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG, PTIME_A>;
308impl<'a, REG> PTIME_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "`0`"]
313    #[inline(always)]
314    pub fn disable(self) -> &'a mut crate::W<REG> {
315        self.variant(PTIME_A::DISABLE)
316    }
317    #[doc = "`1`"]
318    #[inline(always)]
319    pub fn enable(self) -> &'a mut crate::W<REG> {
320        self.variant(PTIME_A::ENABLE)
321    }
322}
323impl R {
324    #[doc = "Bit 0 - Enable Received Data Available Interrupt"]
325    #[inline(always)]
326    pub fn erbfi(&self) -> ERBFI_R {
327        ERBFI_R::new((self.bits & 1) != 0)
328    }
329    #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt"]
330    #[inline(always)]
331    pub fn etbei(&self) -> ETBEI_R {
332        ETBEI_R::new(((self.bits >> 1) & 1) != 0)
333    }
334    #[doc = "Bit 2 - Enable Receiver Line Status Interrupt"]
335    #[inline(always)]
336    pub fn elsi(&self) -> ELSI_R {
337        ELSI_R::new(((self.bits >> 2) & 1) != 0)
338    }
339    #[doc = "Bit 3 - Enable Modem Status Interrupt"]
340    #[inline(always)]
341    pub fn edssi(&self) -> EDSSI_R {
342        EDSSI_R::new(((self.bits >> 3) & 1) != 0)
343    }
344    #[doc = "Bit 4 - RS485 Interrupt Enable"]
345    #[inline(always)]
346    pub fn rs485_int_en(&self) -> RS485_INT_EN_R {
347        RS485_INT_EN_R::new(((self.bits >> 4) & 1) != 0)
348    }
349    #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable"]
350    #[inline(always)]
351    pub fn ptime(&self) -> PTIME_R {
352        PTIME_R::new(((self.bits >> 7) & 1) != 0)
353    }
354}
355impl W {
356    #[doc = "Bit 0 - Enable Received Data Available Interrupt"]
357    #[inline(always)]
358    #[must_use]
359    pub fn erbfi(&mut self) -> ERBFI_W<IER_SPEC> {
360        ERBFI_W::new(self, 0)
361    }
362    #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt"]
363    #[inline(always)]
364    #[must_use]
365    pub fn etbei(&mut self) -> ETBEI_W<IER_SPEC> {
366        ETBEI_W::new(self, 1)
367    }
368    #[doc = "Bit 2 - Enable Receiver Line Status Interrupt"]
369    #[inline(always)]
370    #[must_use]
371    pub fn elsi(&mut self) -> ELSI_W<IER_SPEC> {
372        ELSI_W::new(self, 2)
373    }
374    #[doc = "Bit 3 - Enable Modem Status Interrupt"]
375    #[inline(always)]
376    #[must_use]
377    pub fn edssi(&mut self) -> EDSSI_W<IER_SPEC> {
378        EDSSI_W::new(self, 3)
379    }
380    #[doc = "Bit 4 - RS485 Interrupt Enable"]
381    #[inline(always)]
382    #[must_use]
383    pub fn rs485_int_en(&mut self) -> RS485_INT_EN_W<IER_SPEC> {
384        RS485_INT_EN_W::new(self, 4)
385    }
386    #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable"]
387    #[inline(always)]
388    #[must_use]
389    pub fn ptime(&mut self) -> PTIME_W<IER_SPEC> {
390        PTIME_W::new(self, 7)
391    }
392    #[doc = r" Writes raw bits to the register."]
393    #[doc = r""]
394    #[doc = r" # Safety"]
395    #[doc = r""]
396    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
397    #[inline(always)]
398    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
399        self.bits = bits;
400        self
401    }
402}
403#[doc = "UART Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
404pub struct IER_SPEC;
405impl crate::RegisterSpec for IER_SPEC {
406    type Ux = u32;
407}
408#[doc = "`read()` method returns [`ier::R`](R) reader structure"]
409impl crate::Readable for IER_SPEC {}
410#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
411impl crate::Writable for IER_SPEC {
412    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
413    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
414}
415#[doc = "`reset()` method sets ier to value 0"]
416impl crate::Resettable for IER_SPEC {
417    const RESET_VALUE: Self::Ux = 0;
418}
d1_pac/uart/ier.rs

d1_pac/uart/
ier.rs
