d1_pac/uart/
fcr.rs

1#[doc = "Register `fcr` writer"]
2pub type W = crate::W<FCR_SPEC>;
3#[doc = "Field `fifoe` writer - "]
4pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `rfifor` writer - "]
6pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `xfifor` writer - "]
8pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum DMAM_AW {
12    #[doc = "0: `0`"]
13    MODE_0 = 0,
14    #[doc = "1: `1`"]
15    MODE_1 = 1,
16}
17impl From<DMAM_AW> for bool {
18    #[inline(always)]
19    fn from(variant: DMAM_AW) -> Self {
20        variant as u8 != 0
21    }
22}
23#[doc = "Field `dmam` writer - "]
24pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG, DMAM_AW>;
25impl<'a, REG> DMAM_W<'a, REG>
26where
27    REG: crate::Writable + crate::RegisterSpec,
28{
29    #[doc = "`0`"]
30    #[inline(always)]
31    pub fn mode_0(self) -> &'a mut crate::W<REG> {
32        self.variant(DMAM_AW::MODE_0)
33    }
34    #[doc = "`1`"]
35    #[inline(always)]
36    pub fn mode_1(self) -> &'a mut crate::W<REG> {
37        self.variant(DMAM_AW::MODE_1)
38    }
39}
40#[doc = "\n\nValue on reset: 0"]
41#[derive(Clone, Copy, Debug, PartialEq, Eq)]
42#[repr(u8)]
43pub enum TFT_AW {
44    #[doc = "0: `0`"]
45    EMPTY = 0,
46    #[doc = "1: `1`"]
47    TWO_CHARACTERS = 1,
48    #[doc = "2: `10`"]
49    QUARTER_FULL = 2,
50    #[doc = "3: `11`"]
51    HALF_FULL = 3,
52}
53impl From<TFT_AW> for u8 {
54    #[inline(always)]
55    fn from(variant: TFT_AW) -> Self {
56        variant as _
57    }
58}
59impl crate::FieldSpec for TFT_AW {
60    type Ux = u8;
61}
62#[doc = "Field `tft` writer - "]
63pub type TFT_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, TFT_AW>;
64impl<'a, REG> TFT_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "`0`"]
70    #[inline(always)]
71    pub fn empty(self) -> &'a mut crate::W<REG> {
72        self.variant(TFT_AW::EMPTY)
73    }
74    #[doc = "`1`"]
75    #[inline(always)]
76    pub fn two_characters(self) -> &'a mut crate::W<REG> {
77        self.variant(TFT_AW::TWO_CHARACTERS)
78    }
79    #[doc = "`10`"]
80    #[inline(always)]
81    pub fn quarter_full(self) -> &'a mut crate::W<REG> {
82        self.variant(TFT_AW::QUARTER_FULL)
83    }
84    #[doc = "`11`"]
85    #[inline(always)]
86    pub fn half_full(self) -> &'a mut crate::W<REG> {
87        self.variant(TFT_AW::HALF_FULL)
88    }
89}
90#[doc = "\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92#[repr(u8)]
93pub enum RT_AW {
94    #[doc = "0: `0`"]
95    ONE_CHARACTER = 0,
96    #[doc = "1: `1`"]
97    QUARTER_FULL = 1,
98    #[doc = "2: `10`"]
99    HALF_FULL = 2,
100    #[doc = "3: `11`"]
101    TWO_LESS_THAN_FULL = 3,
102}
103impl From<RT_AW> for u8 {
104    #[inline(always)]
105    fn from(variant: RT_AW) -> Self {
106        variant as _
107    }
108}
109impl crate::FieldSpec for RT_AW {
110    type Ux = u8;
111}
112#[doc = "Field `rt` writer - "]
113pub type RT_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, RT_AW>;
114impl<'a, REG> RT_W<'a, REG>
115where
116    REG: crate::Writable + crate::RegisterSpec,
117    REG::Ux: From<u8>,
118{
119    #[doc = "`0`"]
120    #[inline(always)]
121    pub fn one_character(self) -> &'a mut crate::W<REG> {
122        self.variant(RT_AW::ONE_CHARACTER)
123    }
124    #[doc = "`1`"]
125    #[inline(always)]
126    pub fn quarter_full(self) -> &'a mut crate::W<REG> {
127        self.variant(RT_AW::QUARTER_FULL)
128    }
129    #[doc = "`10`"]
130    #[inline(always)]
131    pub fn half_full(self) -> &'a mut crate::W<REG> {
132        self.variant(RT_AW::HALF_FULL)
133    }
134    #[doc = "`11`"]
135    #[inline(always)]
136    pub fn two_less_than_full(self) -> &'a mut crate::W<REG> {
137        self.variant(RT_AW::TWO_LESS_THAN_FULL)
138    }
139}
140impl W {
141    #[doc = "Bit 0"]
142    #[inline(always)]
143    #[must_use]
144    pub fn fifoe(&mut self) -> FIFOE_W<FCR_SPEC> {
145        FIFOE_W::new(self, 0)
146    }
147    #[doc = "Bit 1"]
148    #[inline(always)]
149    #[must_use]
150    pub fn rfifor(&mut self) -> RFIFOR_W<FCR_SPEC> {
151        RFIFOR_W::new(self, 1)
152    }
153    #[doc = "Bit 2"]
154    #[inline(always)]
155    #[must_use]
156    pub fn xfifor(&mut self) -> XFIFOR_W<FCR_SPEC> {
157        XFIFOR_W::new(self, 2)
158    }
159    #[doc = "Bit 3"]
160    #[inline(always)]
161    #[must_use]
162    pub fn dmam(&mut self) -> DMAM_W<FCR_SPEC> {
163        DMAM_W::new(self, 3)
164    }
165    #[doc = "Bits 4:5"]
166    #[inline(always)]
167    #[must_use]
168    pub fn tft(&mut self) -> TFT_W<FCR_SPEC> {
169        TFT_W::new(self, 4)
170    }
171    #[doc = "Bits 6:7"]
172    #[inline(always)]
173    #[must_use]
174    pub fn rt(&mut self) -> RT_W<FCR_SPEC> {
175        RT_W::new(self, 6)
176    }
177    #[doc = r" Writes raw bits to the register."]
178    #[doc = r""]
179    #[doc = r" # Safety"]
180    #[doc = r""]
181    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
182    #[inline(always)]
183    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
184        self.bits = bits;
185        self
186    }
187}
188#[doc = "UART FIFO Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
189pub struct FCR_SPEC;
190impl crate::RegisterSpec for FCR_SPEC {
191    type Ux = u32;
192}
193#[doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"]
194impl crate::Writable for FCR_SPEC {
195    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
196    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
197}
198#[doc = "`reset()` method sets fcr to value 0"]
199impl crate::Resettable for FCR_SPEC {
200    const RESET_VALUE: Self::Ux = 0;
201}
d1_pac/uart/fcr.rs

d1_pac/uart/
fcr.rs
