d1_pac/uart/
dma_req_en.rs

1#[doc = "Register `dma_req_en` reader"]
2pub type R = crate::R<DMA_REQ_EN_SPEC>;
3#[doc = "Register `dma_req_en` writer"]
4pub type W = crate::W<DMA_REQ_EN_SPEC>;
5#[doc = "Field `rx_req_enable` reader - DMA RX REQ Enable"]
6pub type RX_REQ_ENABLE_R = crate::BitReader<RX_REQ_ENABLE_A>;
7#[doc = "DMA RX REQ Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum RX_REQ_ENABLE_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<RX_REQ_ENABLE_A> for bool {
16    #[inline(always)]
17    fn from(variant: RX_REQ_ENABLE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl RX_REQ_ENABLE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> RX_REQ_ENABLE_A {
25        match self.bits {
26            false => RX_REQ_ENABLE_A::DISABLE,
27            true => RX_REQ_ENABLE_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == RX_REQ_ENABLE_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == RX_REQ_ENABLE_A::ENABLE
39    }
40}
41#[doc = "Field `rx_req_enable` writer - DMA RX REQ Enable"]
42pub type RX_REQ_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, RX_REQ_ENABLE_A>;
43impl<'a, REG> RX_REQ_ENABLE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(RX_REQ_ENABLE_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(RX_REQ_ENABLE_A::ENABLE)
56    }
57}
58#[doc = "Field `tx_req_enable` reader - DMA TX REQ Enable"]
59pub type TX_REQ_ENABLE_R = crate::BitReader<TX_REQ_ENABLE_A>;
60#[doc = "DMA TX REQ Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TX_REQ_ENABLE_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<TX_REQ_ENABLE_A> for bool {
69    #[inline(always)]
70    fn from(variant: TX_REQ_ENABLE_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TX_REQ_ENABLE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TX_REQ_ENABLE_A {
78        match self.bits {
79            false => TX_REQ_ENABLE_A::DISABLE,
80            true => TX_REQ_ENABLE_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == TX_REQ_ENABLE_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == TX_REQ_ENABLE_A::ENABLE
92    }
93}
94#[doc = "Field `tx_req_enable` writer - DMA TX REQ Enable"]
95pub type TX_REQ_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, TX_REQ_ENABLE_A>;
96impl<'a, REG> TX_REQ_ENABLE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(TX_REQ_ENABLE_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(TX_REQ_ENABLE_A::ENABLE)
109    }
110}
111#[doc = "Field `timeout_enable` reader - DMA Timeout Enable"]
112pub type TIMEOUT_ENABLE_R = crate::BitReader<TIMEOUT_ENABLE_A>;
113#[doc = "DMA Timeout Enable\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum TIMEOUT_ENABLE_A {
116    #[doc = "0: `0`"]
117    DISABLE = 0,
118    #[doc = "1: `1`"]
119    ENABLE = 1,
120}
121impl From<TIMEOUT_ENABLE_A> for bool {
122    #[inline(always)]
123    fn from(variant: TIMEOUT_ENABLE_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl TIMEOUT_ENABLE_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> TIMEOUT_ENABLE_A {
131        match self.bits {
132            false => TIMEOUT_ENABLE_A::DISABLE,
133            true => TIMEOUT_ENABLE_A::ENABLE,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == TIMEOUT_ENABLE_A::DISABLE
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == TIMEOUT_ENABLE_A::ENABLE
145    }
146}
147#[doc = "Field `timeout_enable` writer - DMA Timeout Enable"]
148pub type TIMEOUT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, TIMEOUT_ENABLE_A>;
149impl<'a, REG> TIMEOUT_ENABLE_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(TIMEOUT_ENABLE_A::DISABLE)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(TIMEOUT_ENABLE_A::ENABLE)
162    }
163}
164impl R {
165    #[doc = "Bit 0 - DMA RX REQ Enable"]
166    #[inline(always)]
167    pub fn rx_req_enable(&self) -> RX_REQ_ENABLE_R {
168        RX_REQ_ENABLE_R::new((self.bits & 1) != 0)
169    }
170    #[doc = "Bit 1 - DMA TX REQ Enable"]
171    #[inline(always)]
172    pub fn tx_req_enable(&self) -> TX_REQ_ENABLE_R {
173        TX_REQ_ENABLE_R::new(((self.bits >> 1) & 1) != 0)
174    }
175    #[doc = "Bit 2 - DMA Timeout Enable"]
176    #[inline(always)]
177    pub fn timeout_enable(&self) -> TIMEOUT_ENABLE_R {
178        TIMEOUT_ENABLE_R::new(((self.bits >> 2) & 1) != 0)
179    }
180}
181impl W {
182    #[doc = "Bit 0 - DMA RX REQ Enable"]
183    #[inline(always)]
184    #[must_use]
185    pub fn rx_req_enable(&mut self) -> RX_REQ_ENABLE_W<DMA_REQ_EN_SPEC> {
186        RX_REQ_ENABLE_W::new(self, 0)
187    }
188    #[doc = "Bit 1 - DMA TX REQ Enable"]
189    #[inline(always)]
190    #[must_use]
191    pub fn tx_req_enable(&mut self) -> TX_REQ_ENABLE_W<DMA_REQ_EN_SPEC> {
192        TX_REQ_ENABLE_W::new(self, 1)
193    }
194    #[doc = "Bit 2 - DMA Timeout Enable"]
195    #[inline(always)]
196    #[must_use]
197    pub fn timeout_enable(&mut self) -> TIMEOUT_ENABLE_W<DMA_REQ_EN_SPEC> {
198        TIMEOUT_ENABLE_W::new(self, 2)
199    }
200    #[doc = r" Writes raw bits to the register."]
201    #[doc = r""]
202    #[doc = r" # Safety"]
203    #[doc = r""]
204    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
205    #[inline(always)]
206    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
207        self.bits = bits;
208        self
209    }
210}
211#[doc = "UART DMA Request Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct DMA_REQ_EN_SPEC;
213impl crate::RegisterSpec for DMA_REQ_EN_SPEC {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [`dma_req_en::R`](R) reader structure"]
217impl crate::Readable for DMA_REQ_EN_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`dma_req_en::W`](W) writer structure"]
219impl crate::Writable for DMA_REQ_EN_SPEC {
220    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
221    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
222}
223#[doc = "`reset()` method sets dma_req_en to value 0"]
224impl crate::Resettable for DMA_REQ_EN_SPEC {
225    const RESET_VALUE: Self::Ux = 0;
226}
d1_pac/uart/dma_req_en.rs

d1_pac/uart/
dma_req_en.rs
