1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved_0_dll: [u8; 0x04],
5 _reserved_1_dlh: [u8; 0x04],
6 _reserved_2_fcr: [u8; 0x04],
7 lcr: LCR,
8 mcr: MCR,
9 lsr: LSR,
10 msr: MSR,
11 sch: SCH,
12 _reserved8: [u8; 0x5c],
13 usr: USR,
14 tfl: TFL,
15 rfl: RFL,
16 hsk: HSK,
17 dma_req_en: DMA_REQ_EN,
18 _reserved13: [u8; 0x14],
19 halt: HALT,
20 _reserved14: [u8; 0x08],
21 dbg_dll: DBG_DLL,
22 dbg_dlh: DBG_DLH,
23 _reserved16: [u8; 0x38],
24 fcc: FCC,
25 _reserved17: [u8; 0x0c],
26 rxdma_ctrl: RXDMA_CTRL,
27 rxdma_str: RXDMA_STR,
28 rxdma_sta: RXDMA_STA,
29 rxdma_lmt: RXDMA_LMT,
30 rxdma_saddrl: RXDMA_SADDRL,
31 rxdma_saddrh: RXDMA_SADDRH,
32 rxdma_bl: RXDMA_BL,
33 _reserved24: [u8; 0x04],
34 rxdma_ie: RXDMA_IE,
35 rxdma_is: RXDMA_IS,
36 rxdma_waddrl: RXDMA_WADDRL,
37 rxdma_waddrh: RXDMA_WADDRH,
38 rxdma_raddrl: RXDMA_RADDRL,
39 rxdma_raddrh: RXDMA_RADDRH,
40 rxdma_dcnt: RXDMA_DCNT,
41}
42impl RegisterBlock {
43 #[doc = "0x00 - UART Divisor Latch Low Register"]
44 #[inline(always)]
45 pub const fn dll(&self) -> &DLL {
46 unsafe { &*(self as *const Self).cast::<u8>().add(0).cast() }
47 }
48 #[doc = "0x00 - UART Transmit Holding Register"]
49 #[inline(always)]
50 pub const fn thr(&self) -> &THR {
51 unsafe { &*(self as *const Self).cast::<u8>().add(0).cast() }
52 }
53 #[doc = "0x00 - UART Receive Buffer Register"]
54 #[inline(always)]
55 pub const fn rbr(&self) -> &RBR {
56 unsafe { &*(self as *const Self).cast::<u8>().add(0).cast() }
57 }
58 #[doc = "0x04 - UART Interrupt Enable Register"]
59 #[inline(always)]
60 pub const fn ier(&self) -> &IER {
61 unsafe { &*(self as *const Self).cast::<u8>().add(4).cast() }
62 }
63 #[doc = "0x04 - UART Divisor Latch High Register"]
64 #[inline(always)]
65 pub const fn dlh(&self) -> &DLH {
66 unsafe { &*(self as *const Self).cast::<u8>().add(4).cast() }
67 }
68 #[doc = "0x08 - UART FIFO Control Register"]
69 #[inline(always)]
70 pub const fn fcr(&self) -> &FCR {
71 unsafe { &*(self as *const Self).cast::<u8>().add(8).cast() }
72 }
73 #[doc = "0x08 - UART Interrupt Identity Register"]
74 #[inline(always)]
75 pub const fn iir(&self) -> &IIR {
76 unsafe { &*(self as *const Self).cast::<u8>().add(8).cast() }
77 }
78 #[doc = "0x0c - UART Line Control Register"]
79 #[inline(always)]
80 pub const fn lcr(&self) -> &LCR {
81 &self.lcr
82 }
83 #[doc = "0x10 - UART Modem Control Register"]
84 #[inline(always)]
85 pub const fn mcr(&self) -> &MCR {
86 &self.mcr
87 }
88 #[doc = "0x14 - UART Line Status Register"]
89 #[inline(always)]
90 pub const fn lsr(&self) -> &LSR {
91 &self.lsr
92 }
93 #[doc = "0x18 - UART Modem Status Register"]
94 #[inline(always)]
95 pub const fn msr(&self) -> &MSR {
96 &self.msr
97 }
98 #[doc = "0x1c - UART Scratch Register"]
99 #[inline(always)]
100 pub const fn sch(&self) -> &SCH {
101 &self.sch
102 }
103 #[doc = "0x7c - UART Status Register"]
104 #[inline(always)]
105 pub const fn usr(&self) -> &USR {
106 &self.usr
107 }
108 #[doc = "0x80 - UART Transmit FIFO Level Register"]
109 #[inline(always)]
110 pub const fn tfl(&self) -> &TFL {
111 &self.tfl
112 }
113 #[doc = "0x84 - UART Receive FIFO Level Register"]
114 #[inline(always)]
115 pub const fn rfl(&self) -> &RFL {
116 &self.rfl
117 }
118 #[doc = "0x88 - UART DMA Handshake Configuration Register"]
119 #[inline(always)]
120 pub const fn hsk(&self) -> &HSK {
121 &self.hsk
122 }
123 #[doc = "0x8c - UART DMA Request Enable Register"]
124 #[inline(always)]
125 pub const fn dma_req_en(&self) -> &DMA_REQ_EN {
126 &self.dma_req_en
127 }
128 #[doc = "0xa4 - UART Halt TX Register"]
129 #[inline(always)]
130 pub const fn halt(&self) -> &HALT {
131 &self.halt
132 }
133 #[doc = "0xb0 - UART Debug DLL Register"]
134 #[inline(always)]
135 pub const fn dbg_dll(&self) -> &DBG_DLL {
136 &self.dbg_dll
137 }
138 #[doc = "0xb4 - UART Debug DLH Register"]
139 #[inline(always)]
140 pub const fn dbg_dlh(&self) -> &DBG_DLH {
141 &self.dbg_dlh
142 }
143 #[doc = "0xf0 - UART FIFO Clock Control Register"]
144 #[inline(always)]
145 pub const fn fcc(&self) -> &FCC {
146 &self.fcc
147 }
148 #[doc = "0x100 - UART RXDMA Control Register"]
149 #[inline(always)]
150 pub const fn rxdma_ctrl(&self) -> &RXDMA_CTRL {
151 &self.rxdma_ctrl
152 }
153 #[doc = "0x104 - UART RXDMA Start Register"]
154 #[inline(always)]
155 pub const fn rxdma_str(&self) -> &RXDMA_STR {
156 &self.rxdma_str
157 }
158 #[doc = "0x108 - UART RXDMA Status Register"]
159 #[inline(always)]
160 pub const fn rxdma_sta(&self) -> &RXDMA_STA {
161 &self.rxdma_sta
162 }
163 #[doc = "0x10c - UART RXDMA Limit Register"]
164 #[inline(always)]
165 pub const fn rxdma_lmt(&self) -> &RXDMA_LMT {
166 &self.rxdma_lmt
167 }
168 #[doc = "0x110 - UART RXDMA Buffer Start Address Low Register"]
169 #[inline(always)]
170 pub const fn rxdma_saddrl(&self) -> &RXDMA_SADDRL {
171 &self.rxdma_saddrl
172 }
173 #[doc = "0x114 - UART RXDMA Buffer Start Address High Register"]
174 #[inline(always)]
175 pub const fn rxdma_saddrh(&self) -> &RXDMA_SADDRH {
176 &self.rxdma_saddrh
177 }
178 #[doc = "0x118 - UART RXDMA Buffer Length Register"]
179 #[inline(always)]
180 pub const fn rxdma_bl(&self) -> &RXDMA_BL {
181 &self.rxdma_bl
182 }
183 #[doc = "0x120 - UART RXDMA Interrupt Enable Register"]
184 #[inline(always)]
185 pub const fn rxdma_ie(&self) -> &RXDMA_IE {
186 &self.rxdma_ie
187 }
188 #[doc = "0x124 - UART RXDMA Interrupt Status Register"]
189 #[inline(always)]
190 pub const fn rxdma_is(&self) -> &RXDMA_IS {
191 &self.rxdma_is
192 }
193 #[doc = "0x128 - UART RXDMA Write Address Low Register"]
194 #[inline(always)]
195 pub const fn rxdma_waddrl(&self) -> &RXDMA_WADDRL {
196 &self.rxdma_waddrl
197 }
198 #[doc = "0x12c - UART RXDMA Write Address High Register"]
199 #[inline(always)]
200 pub const fn rxdma_waddrh(&self) -> &RXDMA_WADDRH {
201 &self.rxdma_waddrh
202 }
203 #[doc = "0x130 - UART RXDMA Read Address Low Register"]
204 #[inline(always)]
205 pub const fn rxdma_raddrl(&self) -> &RXDMA_RADDRL {
206 &self.rxdma_raddrl
207 }
208 #[doc = "0x134 - UART RXDMA Read Address High Register"]
209 #[inline(always)]
210 pub const fn rxdma_raddrh(&self) -> &RXDMA_RADDRH {
211 &self.rxdma_raddrh
212 }
213 #[doc = "0x138 - UART RXDMA Data Count Register"]
214 #[inline(always)]
215 pub const fn rxdma_dcnt(&self) -> &RXDMA_DCNT {
216 &self.rxdma_dcnt
217 }
218}
219#[doc = "rbr (r) register accessor: UART Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"]
220pub type RBR = crate::Reg<rbr::RBR_SPEC>;
221#[doc = "UART Receive Buffer Register"]
222pub mod rbr;
223#[doc = "thr (w) register accessor: UART Transmit Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"]
224pub type THR = crate::Reg<thr::THR_SPEC>;
225#[doc = "UART Transmit Holding Register"]
226pub mod thr;
227#[doc = "dll (rw) register accessor: UART Divisor Latch Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"]
228pub type DLL = crate::Reg<dll::DLL_SPEC>;
229#[doc = "UART Divisor Latch Low Register"]
230pub mod dll;
231#[doc = "dlh (rw) register accessor: UART Divisor Latch High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"]
232pub type DLH = crate::Reg<dlh::DLH_SPEC>;
233#[doc = "UART Divisor Latch High Register"]
234pub mod dlh;
235#[doc = "ier (rw) register accessor: UART Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"]
236pub type IER = crate::Reg<ier::IER_SPEC>;
237#[doc = "UART Interrupt Enable Register"]
238pub mod ier;
239#[doc = "iir (r) register accessor: UART Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"]
240pub type IIR = crate::Reg<iir::IIR_SPEC>;
241#[doc = "UART Interrupt Identity Register"]
242pub mod iir;
243#[doc = "fcr (w) register accessor: UART FIFO Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"]
244pub type FCR = crate::Reg<fcr::FCR_SPEC>;
245#[doc = "UART FIFO Control Register"]
246pub mod fcr;
247#[doc = "lcr (rw) register accessor: UART Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"]
248pub type LCR = crate::Reg<lcr::LCR_SPEC>;
249#[doc = "UART Line Control Register"]
250pub mod lcr;
251#[doc = "mcr (rw) register accessor: UART Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"]
252pub type MCR = crate::Reg<mcr::MCR_SPEC>;
253#[doc = "UART Modem Control Register"]
254pub mod mcr;
255#[doc = "lsr (r) register accessor: UART Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"]
256pub type LSR = crate::Reg<lsr::LSR_SPEC>;
257#[doc = "UART Line Status Register"]
258pub mod lsr;
259#[doc = "msr (r) register accessor: UART Modem Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"]
260pub type MSR = crate::Reg<msr::MSR_SPEC>;
261#[doc = "UART Modem Status Register"]
262pub mod msr;
263#[doc = "sch (rw) register accessor: UART Scratch Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sch`] module"]
264pub type SCH = crate::Reg<sch::SCH_SPEC>;
265#[doc = "UART Scratch Register"]
266pub mod sch;
267#[doc = "usr (r) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"]
268pub type USR = crate::Reg<usr::USR_SPEC>;
269#[doc = "UART Status Register"]
270pub mod usr;
271#[doc = "tfl (r) register accessor: UART Transmit FIFO Level Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"]
272pub type TFL = crate::Reg<tfl::TFL_SPEC>;
273#[doc = "UART Transmit FIFO Level Register"]
274pub mod tfl;
275#[doc = "rfl (r) register accessor: UART Receive FIFO Level Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"]
276pub type RFL = crate::Reg<rfl::RFL_SPEC>;
277#[doc = "UART Receive FIFO Level Register"]
278pub mod rfl;
279#[doc = "hsk (rw) register accessor: UART DMA Handshake Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hsk`] module"]
280pub type HSK = crate::Reg<hsk::HSK_SPEC>;
281#[doc = "UART DMA Handshake Configuration Register"]
282pub mod hsk;
283#[doc = "dma_req_en (rw) register accessor: UART DMA Request Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_req_en`] module"]
284pub type DMA_REQ_EN = crate::Reg<dma_req_en::DMA_REQ_EN_SPEC>;
285#[doc = "UART DMA Request Enable Register"]
286pub mod dma_req_en;
287#[doc = "halt (rw) register accessor: UART Halt TX Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`halt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`halt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@halt`] module"]
288pub type HALT = crate::Reg<halt::HALT_SPEC>;
289#[doc = "UART Halt TX Register"]
290pub mod halt;
291#[doc = "dbg_dll (r) register accessor: UART Debug DLL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_dll::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbg_dll`] module"]
292pub type DBG_DLL = crate::Reg<dbg_dll::DBG_DLL_SPEC>;
293#[doc = "UART Debug DLL Register"]
294pub mod dbg_dll;
295#[doc = "dbg_dlh (r) register accessor: UART Debug DLH Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_dlh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbg_dlh`] module"]
296pub type DBG_DLH = crate::Reg<dbg_dlh::DBG_DLH_SPEC>;
297#[doc = "UART Debug DLH Register"]
298pub mod dbg_dlh;
299#[doc = "fcc (rw) register accessor: UART FIFO Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcc`] module"]
300pub type FCC = crate::Reg<fcc::FCC_SPEC>;
301#[doc = "UART FIFO Clock Control Register"]
302pub mod fcc;
303#[doc = "rxdma_ctrl (rw) register accessor: UART RXDMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_ctrl`] module"]
304pub type RXDMA_CTRL = crate::Reg<rxdma_ctrl::RXDMA_CTRL_SPEC>;
305#[doc = "UART RXDMA Control Register"]
306pub mod rxdma_ctrl;
307#[doc = "rxdma_str (rw) register accessor: UART RXDMA Start Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_str::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_str::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_str`] module"]
308pub type RXDMA_STR = crate::Reg<rxdma_str::RXDMA_STR_SPEC>;
309#[doc = "UART RXDMA Start Register"]
310pub mod rxdma_str;
311#[doc = "rxdma_sta (rw) register accessor: UART RXDMA Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_sta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_sta`] module"]
312pub type RXDMA_STA = crate::Reg<rxdma_sta::RXDMA_STA_SPEC>;
313#[doc = "UART RXDMA Status Register"]
314pub mod rxdma_sta;
315#[doc = "rxdma_lmt (rw) register accessor: UART RXDMA Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_lmt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_lmt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_lmt`] module"]
316pub type RXDMA_LMT = crate::Reg<rxdma_lmt::RXDMA_LMT_SPEC>;
317#[doc = "UART RXDMA Limit Register"]
318pub mod rxdma_lmt;
319#[doc = "rxdma_saddrl (rw) register accessor: UART RXDMA Buffer Start Address Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_saddrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_saddrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_saddrl`] module"]
320pub type RXDMA_SADDRL = crate::Reg<rxdma_saddrl::RXDMA_SADDRL_SPEC>;
321#[doc = "UART RXDMA Buffer Start Address Low Register"]
322pub mod rxdma_saddrl;
323#[doc = "rxdma_saddrh (rw) register accessor: UART RXDMA Buffer Start Address High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_saddrh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_saddrh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_saddrh`] module"]
324pub type RXDMA_SADDRH = crate::Reg<rxdma_saddrh::RXDMA_SADDRH_SPEC>;
325#[doc = "UART RXDMA Buffer Start Address High Register"]
326pub mod rxdma_saddrh;
327#[doc = "rxdma_bl (rw) register accessor: UART RXDMA Buffer Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_bl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_bl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_bl`] module"]
328pub type RXDMA_BL = crate::Reg<rxdma_bl::RXDMA_BL_SPEC>;
329#[doc = "UART RXDMA Buffer Length Register"]
330pub mod rxdma_bl;
331#[doc = "rxdma_ie (rw) register accessor: UART RXDMA Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_ie::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_ie`] module"]
332pub type RXDMA_IE = crate::Reg<rxdma_ie::RXDMA_IE_SPEC>;
333#[doc = "UART RXDMA Interrupt Enable Register"]
334pub mod rxdma_ie;
335#[doc = "rxdma_is (rw) register accessor: UART RXDMA Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_is::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_is::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_is`] module"]
336pub type RXDMA_IS = crate::Reg<rxdma_is::RXDMA_IS_SPEC>;
337#[doc = "UART RXDMA Interrupt Status Register"]
338pub mod rxdma_is;
339#[doc = "rxdma_waddrl (r) register accessor: UART RXDMA Write Address Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_waddrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_waddrl`] module"]
340pub type RXDMA_WADDRL = crate::Reg<rxdma_waddrl::RXDMA_WADDRL_SPEC>;
341#[doc = "UART RXDMA Write Address Low Register"]
342pub mod rxdma_waddrl;
343#[doc = "rxdma_waddrh (r) register accessor: UART RXDMA Write Address High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_waddrh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_waddrh`] module"]
344pub type RXDMA_WADDRH = crate::Reg<rxdma_waddrh::RXDMA_WADDRH_SPEC>;
345#[doc = "UART RXDMA Write Address High Register"]
346pub mod rxdma_waddrh;
347#[doc = "rxdma_raddrl (rw) register accessor: UART RXDMA Read Address Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_raddrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_raddrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_raddrl`] module"]
348pub type RXDMA_RADDRL = crate::Reg<rxdma_raddrl::RXDMA_RADDRL_SPEC>;
349#[doc = "UART RXDMA Read Address Low Register"]
350pub mod rxdma_raddrl;
351#[doc = "rxdma_raddrh (rw) register accessor: UART RXDMA Read Address High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_raddrh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_raddrh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_raddrh`] module"]
352pub type RXDMA_RADDRH = crate::Reg<rxdma_raddrh::RXDMA_RADDRH_SPEC>;
353#[doc = "UART RXDMA Read Address High Register"]
354pub mod rxdma_raddrh;
355#[doc = "rxdma_dcnt (rw) register accessor: UART RXDMA Data Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdma_dcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxdma_dcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdma_dcnt`] module"]
356pub type RXDMA_DCNT = crate::Reg<rxdma_dcnt::RXDMA_DCNT_SPEC>;
357#[doc = "UART RXDMA Data Count Register"]
358pub mod rxdma_dcnt;