d1_pac/twi/
twi_lcr.rs

1#[doc = "Register `twi_lcr` reader"]
2pub type R = crate::R<TWI_LCR_SPEC>;
3#[doc = "Register `twi_lcr` writer"]
4pub type W = crate::W<TWI_LCR_SPEC>;
5#[doc = "Field `sda_ctl_en` reader - TWI_SDA Line State Control Enable"]
6pub type SDA_CTL_EN_R = crate::BitReader<SDA_CTL_EN_A>;
7#[doc = "TWI_SDA Line State Control Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum SDA_CTL_EN_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<SDA_CTL_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: SDA_CTL_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl SDA_CTL_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> SDA_CTL_EN_A {
25        match self.bits {
26            false => SDA_CTL_EN_A::DISABLE,
27            true => SDA_CTL_EN_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == SDA_CTL_EN_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == SDA_CTL_EN_A::ENABLE
39    }
40}
41#[doc = "Field `sda_ctl_en` writer - TWI_SDA Line State Control Enable"]
42pub type SDA_CTL_EN_W<'a, REG> = crate::BitWriter<'a, REG, SDA_CTL_EN_A>;
43impl<'a, REG> SDA_CTL_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(SDA_CTL_EN_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(SDA_CTL_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `sda_ctl` reader - TWI_SDA Line State Control Bit"]
59pub type SDA_CTL_R = crate::BitReader<SDA_CTL_A>;
60#[doc = "TWI_SDA Line State Control Bit\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum SDA_CTL_A {
63    #[doc = "0: `0`"]
64    LOW = 0,
65    #[doc = "1: `1`"]
66    HIGH = 1,
67}
68impl From<SDA_CTL_A> for bool {
69    #[inline(always)]
70    fn from(variant: SDA_CTL_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl SDA_CTL_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> SDA_CTL_A {
78        match self.bits {
79            false => SDA_CTL_A::LOW,
80            true => SDA_CTL_A::HIGH,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_low(&self) -> bool {
86        *self == SDA_CTL_A::LOW
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_high(&self) -> bool {
91        *self == SDA_CTL_A::HIGH
92    }
93}
94#[doc = "Field `sda_ctl` writer - TWI_SDA Line State Control Bit"]
95pub type SDA_CTL_W<'a, REG> = crate::BitWriter<'a, REG, SDA_CTL_A>;
96impl<'a, REG> SDA_CTL_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn low(self) -> &'a mut crate::W<REG> {
103        self.variant(SDA_CTL_A::LOW)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn high(self) -> &'a mut crate::W<REG> {
108        self.variant(SDA_CTL_A::HIGH)
109    }
110}
111#[doc = "Field `scl_ctl_en` reader - TWI_SCL Line State Control Enable"]
112pub type SCL_CTL_EN_R = crate::BitReader<SCL_CTL_EN_A>;
113#[doc = "TWI_SCL Line State Control Enable\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum SCL_CTL_EN_A {
116    #[doc = "0: `0`"]
117    DISABLE = 0,
118    #[doc = "1: `1`"]
119    ENABLE = 1,
120}
121impl From<SCL_CTL_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: SCL_CTL_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl SCL_CTL_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> SCL_CTL_EN_A {
131        match self.bits {
132            false => SCL_CTL_EN_A::DISABLE,
133            true => SCL_CTL_EN_A::ENABLE,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == SCL_CTL_EN_A::DISABLE
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == SCL_CTL_EN_A::ENABLE
145    }
146}
147#[doc = "Field `scl_ctl_en` writer - TWI_SCL Line State Control Enable"]
148pub type SCL_CTL_EN_W<'a, REG> = crate::BitWriter<'a, REG, SCL_CTL_EN_A>;
149impl<'a, REG> SCL_CTL_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(SCL_CTL_EN_A::DISABLE)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(SCL_CTL_EN_A::ENABLE)
162    }
163}
164#[doc = "Field `scl_ctl` reader - TWI_SCL Line State Control Bit"]
165pub type SCL_CTL_R = crate::BitReader<SCL_CTL_A>;
166#[doc = "TWI_SCL Line State Control Bit\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum SCL_CTL_A {
169    #[doc = "0: `0`"]
170    LOW = 0,
171    #[doc = "1: `1`"]
172    HIGH = 1,
173}
174impl From<SCL_CTL_A> for bool {
175    #[inline(always)]
176    fn from(variant: SCL_CTL_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl SCL_CTL_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> SCL_CTL_A {
184        match self.bits {
185            false => SCL_CTL_A::LOW,
186            true => SCL_CTL_A::HIGH,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_low(&self) -> bool {
192        *self == SCL_CTL_A::LOW
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_high(&self) -> bool {
197        *self == SCL_CTL_A::HIGH
198    }
199}
200#[doc = "Field `scl_ctl` writer - TWI_SCL Line State Control Bit"]
201pub type SCL_CTL_W<'a, REG> = crate::BitWriter<'a, REG, SCL_CTL_A>;
202impl<'a, REG> SCL_CTL_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn low(self) -> &'a mut crate::W<REG> {
209        self.variant(SCL_CTL_A::LOW)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn high(self) -> &'a mut crate::W<REG> {
214        self.variant(SCL_CTL_A::HIGH)
215    }
216}
217#[doc = "Field `sda_state` reader - Current State of TWI_SDA"]
218pub type SDA_STATE_R = crate::BitReader<SDA_STATE_A>;
219#[doc = "Current State of TWI_SDA\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum SDA_STATE_A {
222    #[doc = "0: `0`"]
223    LOW = 0,
224    #[doc = "1: `1`"]
225    HIGH = 1,
226}
227impl From<SDA_STATE_A> for bool {
228    #[inline(always)]
229    fn from(variant: SDA_STATE_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl SDA_STATE_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> SDA_STATE_A {
237        match self.bits {
238            false => SDA_STATE_A::LOW,
239            true => SDA_STATE_A::HIGH,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_low(&self) -> bool {
245        *self == SDA_STATE_A::LOW
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_high(&self) -> bool {
250        *self == SDA_STATE_A::HIGH
251    }
252}
253#[doc = "Field `scl_state` reader - Current State of TWI_SCL"]
254pub type SCL_STATE_R = crate::BitReader<SCL_STATE_A>;
255#[doc = "Current State of TWI_SCL\n\nValue on reset: 0"]
256#[derive(Clone, Copy, Debug, PartialEq, Eq)]
257pub enum SCL_STATE_A {
258    #[doc = "0: `0`"]
259    LOW = 0,
260    #[doc = "1: `1`"]
261    HIGH = 1,
262}
263impl From<SCL_STATE_A> for bool {
264    #[inline(always)]
265    fn from(variant: SCL_STATE_A) -> Self {
266        variant as u8 != 0
267    }
268}
269impl SCL_STATE_R {
270    #[doc = "Get enumerated values variant"]
271    #[inline(always)]
272    pub const fn variant(&self) -> SCL_STATE_A {
273        match self.bits {
274            false => SCL_STATE_A::LOW,
275            true => SCL_STATE_A::HIGH,
276        }
277    }
278    #[doc = "`0`"]
279    #[inline(always)]
280    pub fn is_low(&self) -> bool {
281        *self == SCL_STATE_A::LOW
282    }
283    #[doc = "`1`"]
284    #[inline(always)]
285    pub fn is_high(&self) -> bool {
286        *self == SCL_STATE_A::HIGH
287    }
288}
289impl R {
290    #[doc = "Bit 0 - TWI_SDA Line State Control Enable"]
291    #[inline(always)]
292    pub fn sda_ctl_en(&self) -> SDA_CTL_EN_R {
293        SDA_CTL_EN_R::new((self.bits & 1) != 0)
294    }
295    #[doc = "Bit 1 - TWI_SDA Line State Control Bit"]
296    #[inline(always)]
297    pub fn sda_ctl(&self) -> SDA_CTL_R {
298        SDA_CTL_R::new(((self.bits >> 1) & 1) != 0)
299    }
300    #[doc = "Bit 2 - TWI_SCL Line State Control Enable"]
301    #[inline(always)]
302    pub fn scl_ctl_en(&self) -> SCL_CTL_EN_R {
303        SCL_CTL_EN_R::new(((self.bits >> 2) & 1) != 0)
304    }
305    #[doc = "Bit 3 - TWI_SCL Line State Control Bit"]
306    #[inline(always)]
307    pub fn scl_ctl(&self) -> SCL_CTL_R {
308        SCL_CTL_R::new(((self.bits >> 3) & 1) != 0)
309    }
310    #[doc = "Bit 4 - Current State of TWI_SDA"]
311    #[inline(always)]
312    pub fn sda_state(&self) -> SDA_STATE_R {
313        SDA_STATE_R::new(((self.bits >> 4) & 1) != 0)
314    }
315    #[doc = "Bit 5 - Current State of TWI_SCL"]
316    #[inline(always)]
317    pub fn scl_state(&self) -> SCL_STATE_R {
318        SCL_STATE_R::new(((self.bits >> 5) & 1) != 0)
319    }
320}
321impl W {
322    #[doc = "Bit 0 - TWI_SDA Line State Control Enable"]
323    #[inline(always)]
324    #[must_use]
325    pub fn sda_ctl_en(&mut self) -> SDA_CTL_EN_W<TWI_LCR_SPEC> {
326        SDA_CTL_EN_W::new(self, 0)
327    }
328    #[doc = "Bit 1 - TWI_SDA Line State Control Bit"]
329    #[inline(always)]
330    #[must_use]
331    pub fn sda_ctl(&mut self) -> SDA_CTL_W<TWI_LCR_SPEC> {
332        SDA_CTL_W::new(self, 1)
333    }
334    #[doc = "Bit 2 - TWI_SCL Line State Control Enable"]
335    #[inline(always)]
336    #[must_use]
337    pub fn scl_ctl_en(&mut self) -> SCL_CTL_EN_W<TWI_LCR_SPEC> {
338        SCL_CTL_EN_W::new(self, 2)
339    }
340    #[doc = "Bit 3 - TWI_SCL Line State Control Bit"]
341    #[inline(always)]
342    #[must_use]
343    pub fn scl_ctl(&mut self) -> SCL_CTL_W<TWI_LCR_SPEC> {
344        SCL_CTL_W::new(self, 3)
345    }
346    #[doc = r" Writes raw bits to the register."]
347    #[doc = r""]
348    #[doc = r" # Safety"]
349    #[doc = r""]
350    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
351    #[inline(always)]
352    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
353        self.bits = bits;
354        self
355    }
356}
357#[doc = "TWI Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_lcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
358pub struct TWI_LCR_SPEC;
359impl crate::RegisterSpec for TWI_LCR_SPEC {
360    type Ux = u32;
361}
362#[doc = "`read()` method returns [`twi_lcr::R`](R) reader structure"]
363impl crate::Readable for TWI_LCR_SPEC {}
364#[doc = "`write(|w| ..)` method takes [`twi_lcr::W`](W) writer structure"]
365impl crate::Writable for TWI_LCR_SPEC {
366    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
367    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
368}
369#[doc = "`reset()` method sets twi_lcr to value 0"]
370impl crate::Resettable for TWI_LCR_SPEC {
371    const RESET_VALUE: Self::Ux = 0;
372}
d1_pac/twi/twi_lcr.rs

d1_pac/twi/
twi_lcr.rs
