d1_pac/twi/
twi_drv_send_fifo_acc.rs

1#[doc = "Register `twi_drv_send_fifo_acc` writer"]
2pub type W = crate::W<TWI_DRV_SEND_FIFO_ACC_SPEC>;
3#[doc = "Field `send_data_fifo` writer - "]
4pub type SEND_DATA_FIFO_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
5impl W {
6    #[doc = "Bits 0:7"]
7    #[inline(always)]
8    #[must_use]
9    pub fn send_data_fifo(&mut self) -> SEND_DATA_FIFO_W<TWI_DRV_SEND_FIFO_ACC_SPEC> {
10        SEND_DATA_FIFO_W::new(self, 0)
11    }
12    #[doc = r" Writes raw bits to the register."]
13    #[doc = r""]
14    #[doc = r" # Safety"]
15    #[doc = r""]
16    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
17    #[inline(always)]
18    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
19        self.bits = bits;
20        self
21    }
22}
23#[doc = "TWI_DRV Send Data FIFO Access Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_drv_send_fifo_acc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24pub struct TWI_DRV_SEND_FIFO_ACC_SPEC;
25impl crate::RegisterSpec for TWI_DRV_SEND_FIFO_ACC_SPEC {
26    type Ux = u32;
27}
28#[doc = "`write(|w| ..)` method takes [`twi_drv_send_fifo_acc::W`](W) writer structure"]
29impl crate::Writable for TWI_DRV_SEND_FIFO_ACC_SPEC {
30    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
31    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
32}
33#[doc = "`reset()` method sets twi_drv_send_fifo_acc to value 0"]
34impl crate::Resettable for TWI_DRV_SEND_FIFO_ACC_SPEC {
35    const RESET_VALUE: Self::Ux = 0;
36}
d1_pac/twi/twi_drv_send_fifo_acc.rs

d1_pac/twi/
twi_drv_send_fifo_acc.rs
