d1_pac/twi/
twi_drv_recv_fifo_acc.rs

1#[doc = "Register `twi_drv_recv_fifo_acc` reader"]
2pub type R = crate::R<TWI_DRV_RECV_FIFO_ACC_SPEC>;
3#[doc = "Field `recv_data_fifo` reader - "]
4pub type RECV_DATA_FIFO_R = crate::FieldReader;
5impl R {
6    #[doc = "Bits 0:7"]
7    #[inline(always)]
8    pub fn recv_data_fifo(&self) -> RECV_DATA_FIFO_R {
9        RECV_DATA_FIFO_R::new((self.bits & 0xff) as u8)
10    }
11}
12#[doc = "TWI_DRV Receive Data FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_drv_recv_fifo_acc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13pub struct TWI_DRV_RECV_FIFO_ACC_SPEC;
14impl crate::RegisterSpec for TWI_DRV_RECV_FIFO_ACC_SPEC {
15    type Ux = u32;
16}
17#[doc = "`read()` method returns [`twi_drv_recv_fifo_acc::R`](R) reader structure"]
18impl crate::Readable for TWI_DRV_RECV_FIFO_ACC_SPEC {}
19#[doc = "`reset()` method sets twi_drv_recv_fifo_acc to value 0"]
20impl crate::Resettable for TWI_DRV_RECV_FIFO_ACC_SPEC {
21    const RESET_VALUE: Self::Ux = 0;
22}