d1_pac/twi/
twi_drv_int_ctrl.rs

1#[doc = "Register `twi_drv_int_ctrl` reader"]
2pub type R = crate::R<TWI_DRV_INT_CTRL_SPEC>;
3#[doc = "Register `twi_drv_int_ctrl` writer"]
4pub type W = crate::W<TWI_DRV_INT_CTRL_SPEC>;
5#[doc = "Field `tran_com_pd` reader - "]
6pub type TRAN_COM_PD_R = crate::BitReader;
7#[doc = "Field `tran_com_pd` writer - "]
8pub type TRAN_COM_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `tran_err_pd` reader - "]
10pub type TRAN_ERR_PD_R = crate::BitReader;
11#[doc = "Field `tran_err_pd` writer - "]
12pub type TRAN_ERR_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `tx_req_pd` reader - "]
14pub type TX_REQ_PD_R = crate::BitReader;
15#[doc = "Field `tx_req_pd` writer - "]
16pub type TX_REQ_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `rx_req_pd` reader - "]
18pub type RX_REQ_PD_R = crate::BitReader;
19#[doc = "Field `rx_req_pd` writer - "]
20pub type RX_REQ_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `tran_com_int_en` reader - "]
22pub type TRAN_COM_INT_EN_R = crate::BitReader;
23#[doc = "Field `tran_com_int_en` writer - "]
24pub type TRAN_COM_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `tran_err_int_en` reader - "]
26pub type TRAN_ERR_INT_EN_R = crate::BitReader;
27#[doc = "Field `tran_err_int_en` writer - "]
28pub type TRAN_ERR_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `tx_req_int_en` reader - "]
30pub type TX_REQ_INT_EN_R = crate::BitReader;
31#[doc = "Field `tx_req_int_en` writer - "]
32pub type TX_REQ_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `rx_req_int_en` reader - "]
34pub type RX_REQ_INT_EN_R = crate::BitReader;
35#[doc = "Field `rx_req_int_en` writer - "]
36pub type RX_REQ_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bit 0"]
39    #[inline(always)]
40    pub fn tran_com_pd(&self) -> TRAN_COM_PD_R {
41        TRAN_COM_PD_R::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1"]
44    #[inline(always)]
45    pub fn tran_err_pd(&self) -> TRAN_ERR_PD_R {
46        TRAN_ERR_PD_R::new(((self.bits >> 1) & 1) != 0)
47    }
48    #[doc = "Bit 2"]
49    #[inline(always)]
50    pub fn tx_req_pd(&self) -> TX_REQ_PD_R {
51        TX_REQ_PD_R::new(((self.bits >> 2) & 1) != 0)
52    }
53    #[doc = "Bit 3"]
54    #[inline(always)]
55    pub fn rx_req_pd(&self) -> RX_REQ_PD_R {
56        RX_REQ_PD_R::new(((self.bits >> 3) & 1) != 0)
57    }
58    #[doc = "Bit 16"]
59    #[inline(always)]
60    pub fn tran_com_int_en(&self) -> TRAN_COM_INT_EN_R {
61        TRAN_COM_INT_EN_R::new(((self.bits >> 16) & 1) != 0)
62    }
63    #[doc = "Bit 17"]
64    #[inline(always)]
65    pub fn tran_err_int_en(&self) -> TRAN_ERR_INT_EN_R {
66        TRAN_ERR_INT_EN_R::new(((self.bits >> 17) & 1) != 0)
67    }
68    #[doc = "Bit 18"]
69    #[inline(always)]
70    pub fn tx_req_int_en(&self) -> TX_REQ_INT_EN_R {
71        TX_REQ_INT_EN_R::new(((self.bits >> 18) & 1) != 0)
72    }
73    #[doc = "Bit 19"]
74    #[inline(always)]
75    pub fn rx_req_int_en(&self) -> RX_REQ_INT_EN_R {
76        RX_REQ_INT_EN_R::new(((self.bits >> 19) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bit 0"]
81    #[inline(always)]
82    #[must_use]
83    pub fn tran_com_pd(&mut self) -> TRAN_COM_PD_W<TWI_DRV_INT_CTRL_SPEC> {
84        TRAN_COM_PD_W::new(self, 0)
85    }
86    #[doc = "Bit 1"]
87    #[inline(always)]
88    #[must_use]
89    pub fn tran_err_pd(&mut self) -> TRAN_ERR_PD_W<TWI_DRV_INT_CTRL_SPEC> {
90        TRAN_ERR_PD_W::new(self, 1)
91    }
92    #[doc = "Bit 2"]
93    #[inline(always)]
94    #[must_use]
95    pub fn tx_req_pd(&mut self) -> TX_REQ_PD_W<TWI_DRV_INT_CTRL_SPEC> {
96        TX_REQ_PD_W::new(self, 2)
97    }
98    #[doc = "Bit 3"]
99    #[inline(always)]
100    #[must_use]
101    pub fn rx_req_pd(&mut self) -> RX_REQ_PD_W<TWI_DRV_INT_CTRL_SPEC> {
102        RX_REQ_PD_W::new(self, 3)
103    }
104    #[doc = "Bit 16"]
105    #[inline(always)]
106    #[must_use]
107    pub fn tran_com_int_en(&mut self) -> TRAN_COM_INT_EN_W<TWI_DRV_INT_CTRL_SPEC> {
108        TRAN_COM_INT_EN_W::new(self, 16)
109    }
110    #[doc = "Bit 17"]
111    #[inline(always)]
112    #[must_use]
113    pub fn tran_err_int_en(&mut self) -> TRAN_ERR_INT_EN_W<TWI_DRV_INT_CTRL_SPEC> {
114        TRAN_ERR_INT_EN_W::new(self, 17)
115    }
116    #[doc = "Bit 18"]
117    #[inline(always)]
118    #[must_use]
119    pub fn tx_req_int_en(&mut self) -> TX_REQ_INT_EN_W<TWI_DRV_INT_CTRL_SPEC> {
120        TX_REQ_INT_EN_W::new(self, 18)
121    }
122    #[doc = "Bit 19"]
123    #[inline(always)]
124    #[must_use]
125    pub fn rx_req_int_en(&mut self) -> RX_REQ_INT_EN_W<TWI_DRV_INT_CTRL_SPEC> {
126        RX_REQ_INT_EN_W::new(self, 19)
127    }
128    #[doc = r" Writes raw bits to the register."]
129    #[doc = r""]
130    #[doc = r" # Safety"]
131    #[doc = r""]
132    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
133    #[inline(always)]
134    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
135        self.bits = bits;
136        self
137    }
138}
139#[doc = "TWI_DRV Interrupt Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_drv_int_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_drv_int_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
140pub struct TWI_DRV_INT_CTRL_SPEC;
141impl crate::RegisterSpec for TWI_DRV_INT_CTRL_SPEC {
142    type Ux = u32;
143}
144#[doc = "`read()` method returns [`twi_drv_int_ctrl::R`](R) reader structure"]
145impl crate::Readable for TWI_DRV_INT_CTRL_SPEC {}
146#[doc = "`write(|w| ..)` method takes [`twi_drv_int_ctrl::W`](W) writer structure"]
147impl crate::Writable for TWI_DRV_INT_CTRL_SPEC {
148    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
149    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150}
151#[doc = "`reset()` method sets twi_drv_int_ctrl to value 0"]
152impl crate::Resettable for TWI_DRV_INT_CTRL_SPEC {
153    const RESET_VALUE: Self::Ux = 0;
154}
d1_pac/twi/twi_drv_int_ctrl.rs

d1_pac/twi/
twi_drv_int_ctrl.rs
