d1_pac/twi/
twi_drv_fifo_con.rs

1#[doc = "Register `twi_drv_fifo_con` reader"]
2pub type R = crate::R<TWI_DRV_FIFO_CON_SPEC>;
3#[doc = "Register `twi_drv_fifo_con` writer"]
4pub type W = crate::W<TWI_DRV_FIFO_CON_SPEC>;
5#[doc = "Field `send_fifo_content` reader - "]
6pub type SEND_FIFO_CONTENT_R = crate::FieldReader;
7#[doc = "Field `send_fifo_content` writer - "]
8pub type SEND_FIFO_CONTENT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `send_fifo_clear` reader - "]
10pub type SEND_FIFO_CLEAR_R = crate::BitReader;
11#[doc = "Field `send_fifo_clear` writer - "]
12pub type SEND_FIFO_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `recv_fifo_content` reader - "]
14pub type RECV_FIFO_CONTENT_R = crate::FieldReader;
15#[doc = "Field `recv_fifo_content` writer - "]
16pub type RECV_FIFO_CONTENT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `recv_fifo_clear` reader - "]
18pub type RECV_FIFO_CLEAR_R = crate::BitReader;
19#[doc = "Field `recv_fifo_clear` writer - "]
20pub type RECV_FIFO_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:5"]
23    #[inline(always)]
24    pub fn send_fifo_content(&self) -> SEND_FIFO_CONTENT_R {
25        SEND_FIFO_CONTENT_R::new((self.bits & 0x3f) as u8)
26    }
27    #[doc = "Bit 6"]
28    #[inline(always)]
29    pub fn send_fifo_clear(&self) -> SEND_FIFO_CLEAR_R {
30        SEND_FIFO_CLEAR_R::new(((self.bits >> 6) & 1) != 0)
31    }
32    #[doc = "Bits 16:21"]
33    #[inline(always)]
34    pub fn recv_fifo_content(&self) -> RECV_FIFO_CONTENT_R {
35        RECV_FIFO_CONTENT_R::new(((self.bits >> 16) & 0x3f) as u8)
36    }
37    #[doc = "Bit 22"]
38    #[inline(always)]
39    pub fn recv_fifo_clear(&self) -> RECV_FIFO_CLEAR_R {
40        RECV_FIFO_CLEAR_R::new(((self.bits >> 22) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bits 0:5"]
45    #[inline(always)]
46    #[must_use]
47    pub fn send_fifo_content(&mut self) -> SEND_FIFO_CONTENT_W<TWI_DRV_FIFO_CON_SPEC> {
48        SEND_FIFO_CONTENT_W::new(self, 0)
49    }
50    #[doc = "Bit 6"]
51    #[inline(always)]
52    #[must_use]
53    pub fn send_fifo_clear(&mut self) -> SEND_FIFO_CLEAR_W<TWI_DRV_FIFO_CON_SPEC> {
54        SEND_FIFO_CLEAR_W::new(self, 6)
55    }
56    #[doc = "Bits 16:21"]
57    #[inline(always)]
58    #[must_use]
59    pub fn recv_fifo_content(&mut self) -> RECV_FIFO_CONTENT_W<TWI_DRV_FIFO_CON_SPEC> {
60        RECV_FIFO_CONTENT_W::new(self, 16)
61    }
62    #[doc = "Bit 22"]
63    #[inline(always)]
64    #[must_use]
65    pub fn recv_fifo_clear(&mut self) -> RECV_FIFO_CLEAR_W<TWI_DRV_FIFO_CON_SPEC> {
66        RECV_FIFO_CLEAR_W::new(self, 22)
67    }
68    #[doc = r" Writes raw bits to the register."]
69    #[doc = r""]
70    #[doc = r" # Safety"]
71    #[doc = r""]
72    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.bits = bits;
76        self
77    }
78}
79#[doc = "TWI_DRV FIFO Content Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_drv_fifo_con::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_drv_fifo_con::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct TWI_DRV_FIFO_CON_SPEC;
81impl crate::RegisterSpec for TWI_DRV_FIFO_CON_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`twi_drv_fifo_con::R`](R) reader structure"]
85impl crate::Readable for TWI_DRV_FIFO_CON_SPEC {}
86#[doc = "`write(|w| ..)` method takes [`twi_drv_fifo_con::W`](W) writer structure"]
87impl crate::Writable for TWI_DRV_FIFO_CON_SPEC {
88    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
89    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
90}
91#[doc = "`reset()` method sets twi_drv_fifo_con to value 0"]
92impl crate::Resettable for TWI_DRV_FIFO_CON_SPEC {
93    const RESET_VALUE: Self::Ux = 0;
94}
d1_pac/twi/twi_drv_fifo_con.rs

d1_pac/twi/
twi_drv_fifo_con.rs
