d1_pac/twi/
twi_drv_ctrl.rs

1#[doc = "Register `twi_drv_ctrl` reader"]
2pub type R = crate::R<TWI_DRV_CTRL_SPEC>;
3#[doc = "Register `twi_drv_ctrl` writer"]
4pub type W = crate::W<TWI_DRV_CTRL_SPEC>;
5#[doc = "Field `twi_drv_en` reader - "]
6pub type TWI_DRV_EN_R = crate::BitReader<TWI_DRV_EN_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TWI_DRV_EN_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<TWI_DRV_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: TWI_DRV_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TWI_DRV_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TWI_DRV_EN_A {
25        match self.bits {
26            false => TWI_DRV_EN_A::DISABLE,
27            true => TWI_DRV_EN_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == TWI_DRV_EN_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == TWI_DRV_EN_A::ENABLE
39    }
40}
41#[doc = "Field `twi_drv_en` writer - "]
42pub type TWI_DRV_EN_W<'a, REG> = crate::BitWriter<'a, REG, TWI_DRV_EN_A>;
43impl<'a, REG> TWI_DRV_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(TWI_DRV_EN_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(TWI_DRV_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `soft_reset` reader - Software reset"]
59pub type SOFT_RESET_R = crate::BitReader<SOFT_RESET_A>;
60#[doc = "Software reset\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum SOFT_RESET_A {
63    #[doc = "0: `0`"]
64    NORMAL = 0,
65    #[doc = "1: `1`"]
66    RESET = 1,
67}
68impl From<SOFT_RESET_A> for bool {
69    #[inline(always)]
70    fn from(variant: SOFT_RESET_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl SOFT_RESET_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> SOFT_RESET_A {
78        match self.bits {
79            false => SOFT_RESET_A::NORMAL,
80            true => SOFT_RESET_A::RESET,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_normal(&self) -> bool {
86        *self == SOFT_RESET_A::NORMAL
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_reset(&self) -> bool {
91        *self == SOFT_RESET_A::RESET
92    }
93}
94#[doc = "Field `soft_reset` writer - Software reset"]
95pub type SOFT_RESET_W<'a, REG> = crate::BitWriter<'a, REG, SOFT_RESET_A>;
96impl<'a, REG> SOFT_RESET_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn normal(self) -> &'a mut crate::W<REG> {
103        self.variant(SOFT_RESET_A::NORMAL)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn reset(self) -> &'a mut crate::W<REG> {
108        self.variant(SOFT_RESET_A::RESET)
109    }
110}
111#[doc = "Field `timeout_n` reader - Timeout number"]
112pub type TIMEOUT_N_R = crate::FieldReader;
113#[doc = "Field `timeout_n` writer - Timeout number"]
114pub type TIMEOUT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
115#[doc = "Field `twi_sta` reader - TWI status"]
116pub type TWI_STA_R = crate::FieldReader<TWI_STA_A>;
117#[doc = "TWI status\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119#[repr(u8)]
120pub enum TWI_STA_A {
121    #[doc = "0: bus error"]
122    BE = 0,
123    #[doc = "8: START condition transmitted"]
124    SCT = 8,
125    #[doc = "16: Repeated START condition transmitted"]
126    RSCT = 16,
127    #[doc = "24: Address + Write bit transmitted, ACK received"]
128    AWBT_AR = 24,
129    #[doc = "32: Address + Write bit transmitted, ACK not received"]
130    AWBT_ANR = 32,
131    #[doc = "40: Data byte transmitted in master mode, ACK received"]
132    DBTM_AR = 40,
133    #[doc = "48: Data byte transmitted in master mode, ACK not received"]
134    DBTM_ANR = 48,
135    #[doc = "56: Arbitration lost in address or data byte"]
136    AL_A_DB = 56,
137    #[doc = "64: Address + Read bit transmitted, ACK received"]
138    ARBT_AR = 64,
139    #[doc = "72: Address + Read bit transmitted, ACK not received"]
140    ARBT_ANR = 72,
141    #[doc = "80: Data byte received in master mode, ACK received"]
142    DBRM_AR = 80,
143    #[doc = "88: Data byte received in master mode, ACK not received"]
144    DBRM_ANR = 88,
145    #[doc = "1: Timeout when sending the 9th SCL clock"]
146    T_S9SC = 1,
147}
148impl From<TWI_STA_A> for u8 {
149    #[inline(always)]
150    fn from(variant: TWI_STA_A) -> Self {
151        variant as _
152    }
153}
154impl crate::FieldSpec for TWI_STA_A {
155    type Ux = u8;
156}
157impl TWI_STA_R {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub const fn variant(&self) -> Option<TWI_STA_A> {
161        match self.bits {
162            0 => Some(TWI_STA_A::BE),
163            8 => Some(TWI_STA_A::SCT),
164            16 => Some(TWI_STA_A::RSCT),
165            24 => Some(TWI_STA_A::AWBT_AR),
166            32 => Some(TWI_STA_A::AWBT_ANR),
167            40 => Some(TWI_STA_A::DBTM_AR),
168            48 => Some(TWI_STA_A::DBTM_ANR),
169            56 => Some(TWI_STA_A::AL_A_DB),
170            64 => Some(TWI_STA_A::ARBT_AR),
171            72 => Some(TWI_STA_A::ARBT_ANR),
172            80 => Some(TWI_STA_A::DBRM_AR),
173            88 => Some(TWI_STA_A::DBRM_ANR),
174            1 => Some(TWI_STA_A::T_S9SC),
175            _ => None,
176        }
177    }
178    #[doc = "bus error"]
179    #[inline(always)]
180    pub fn is_be(&self) -> bool {
181        *self == TWI_STA_A::BE
182    }
183    #[doc = "START condition transmitted"]
184    #[inline(always)]
185    pub fn is_sct(&self) -> bool {
186        *self == TWI_STA_A::SCT
187    }
188    #[doc = "Repeated START condition transmitted"]
189    #[inline(always)]
190    pub fn is_rsct(&self) -> bool {
191        *self == TWI_STA_A::RSCT
192    }
193    #[doc = "Address + Write bit transmitted, ACK received"]
194    #[inline(always)]
195    pub fn is_awbt_ar(&self) -> bool {
196        *self == TWI_STA_A::AWBT_AR
197    }
198    #[doc = "Address + Write bit transmitted, ACK not received"]
199    #[inline(always)]
200    pub fn is_awbt_anr(&self) -> bool {
201        *self == TWI_STA_A::AWBT_ANR
202    }
203    #[doc = "Data byte transmitted in master mode, ACK received"]
204    #[inline(always)]
205    pub fn is_dbtm_ar(&self) -> bool {
206        *self == TWI_STA_A::DBTM_AR
207    }
208    #[doc = "Data byte transmitted in master mode, ACK not received"]
209    #[inline(always)]
210    pub fn is_dbtm_anr(&self) -> bool {
211        *self == TWI_STA_A::DBTM_ANR
212    }
213    #[doc = "Arbitration lost in address or data byte"]
214    #[inline(always)]
215    pub fn is_al_a_db(&self) -> bool {
216        *self == TWI_STA_A::AL_A_DB
217    }
218    #[doc = "Address + Read bit transmitted, ACK received"]
219    #[inline(always)]
220    pub fn is_arbt_ar(&self) -> bool {
221        *self == TWI_STA_A::ARBT_AR
222    }
223    #[doc = "Address + Read bit transmitted, ACK not received"]
224    #[inline(always)]
225    pub fn is_arbt_anr(&self) -> bool {
226        *self == TWI_STA_A::ARBT_ANR
227    }
228    #[doc = "Data byte received in master mode, ACK received"]
229    #[inline(always)]
230    pub fn is_dbrm_ar(&self) -> bool {
231        *self == TWI_STA_A::DBRM_AR
232    }
233    #[doc = "Data byte received in master mode, ACK not received"]
234    #[inline(always)]
235    pub fn is_dbrm_anr(&self) -> bool {
236        *self == TWI_STA_A::DBRM_ANR
237    }
238    #[doc = "Timeout when sending the 9th SCL clock"]
239    #[inline(always)]
240    pub fn is_t_s9sc(&self) -> bool {
241        *self == TWI_STA_A::T_S9SC
242    }
243}
244#[doc = "Field `tran_result` reader - Transition result"]
245pub type TRAN_RESULT_R = crate::FieldReader<TRAN_RESULT_A>;
246#[doc = "Transition result\n\nValue on reset: 0"]
247#[derive(Clone, Copy, Debug, PartialEq, Eq)]
248#[repr(u8)]
249pub enum TRAN_RESULT_A {
250    #[doc = "0: `0`"]
251    OK = 0,
252    #[doc = "1: `1`"]
253    FAIL = 1,
254}
255impl From<TRAN_RESULT_A> for u8 {
256    #[inline(always)]
257    fn from(variant: TRAN_RESULT_A) -> Self {
258        variant as _
259    }
260}
261impl crate::FieldSpec for TRAN_RESULT_A {
262    type Ux = u8;
263}
264impl TRAN_RESULT_R {
265    #[doc = "Get enumerated values variant"]
266    #[inline(always)]
267    pub const fn variant(&self) -> Option<TRAN_RESULT_A> {
268        match self.bits {
269            0 => Some(TRAN_RESULT_A::OK),
270            1 => Some(TRAN_RESULT_A::FAIL),
271            _ => None,
272        }
273    }
274    #[doc = "`0`"]
275    #[inline(always)]
276    pub fn is_ok(&self) -> bool {
277        *self == TRAN_RESULT_A::OK
278    }
279    #[doc = "`1`"]
280    #[inline(always)]
281    pub fn is_fail(&self) -> bool {
282        *self == TRAN_RESULT_A::FAIL
283    }
284}
285#[doc = "Field `tran_result` writer - Transition result"]
286pub type TRAN_RESULT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, TRAN_RESULT_A>;
287impl<'a, REG> TRAN_RESULT_W<'a, REG>
288where
289    REG: crate::Writable + crate::RegisterSpec,
290    REG::Ux: From<u8>,
291{
292    #[doc = "`0`"]
293    #[inline(always)]
294    pub fn ok(self) -> &'a mut crate::W<REG> {
295        self.variant(TRAN_RESULT_A::OK)
296    }
297    #[doc = "`1`"]
298    #[inline(always)]
299    pub fn fail(self) -> &'a mut crate::W<REG> {
300        self.variant(TRAN_RESULT_A::FAIL)
301    }
302}
303#[doc = "Field `read_tran_mode` reader - Read transition mode"]
304pub type READ_TRAN_MODE_R = crate::BitReader<READ_TRAN_MODE_A>;
305#[doc = "Read transition mode\n\nValue on reset: 0"]
306#[derive(Clone, Copy, Debug, PartialEq, Eq)]
307pub enum READ_TRAN_MODE_A {
308    #[doc = "0: `0`"]
309    SEND = 0,
310    #[doc = "1: `1`"]
311    NOT_SEND = 1,
312}
313impl From<READ_TRAN_MODE_A> for bool {
314    #[inline(always)]
315    fn from(variant: READ_TRAN_MODE_A) -> Self {
316        variant as u8 != 0
317    }
318}
319impl READ_TRAN_MODE_R {
320    #[doc = "Get enumerated values variant"]
321    #[inline(always)]
322    pub const fn variant(&self) -> READ_TRAN_MODE_A {
323        match self.bits {
324            false => READ_TRAN_MODE_A::SEND,
325            true => READ_TRAN_MODE_A::NOT_SEND,
326        }
327    }
328    #[doc = "`0`"]
329    #[inline(always)]
330    pub fn is_send(&self) -> bool {
331        *self == READ_TRAN_MODE_A::SEND
332    }
333    #[doc = "`1`"]
334    #[inline(always)]
335    pub fn is_not_send(&self) -> bool {
336        *self == READ_TRAN_MODE_A::NOT_SEND
337    }
338}
339#[doc = "Field `read_tran_mode` writer - Read transition mode"]
340pub type READ_TRAN_MODE_W<'a, REG> = crate::BitWriter<'a, REG, READ_TRAN_MODE_A>;
341impl<'a, REG> READ_TRAN_MODE_W<'a, REG>
342where
343    REG: crate::Writable + crate::RegisterSpec,
344{
345    #[doc = "`0`"]
346    #[inline(always)]
347    pub fn send(self) -> &'a mut crate::W<REG> {
348        self.variant(READ_TRAN_MODE_A::SEND)
349    }
350    #[doc = "`1`"]
351    #[inline(always)]
352    pub fn not_send(self) -> &'a mut crate::W<REG> {
353        self.variant(READ_TRAN_MODE_A::NOT_SEND)
354    }
355}
356#[doc = "Field `restart_mode` reader - Restart mode"]
357pub type RESTART_MODE_R = crate::BitReader<RESTART_MODE_A>;
358#[doc = "Restart mode\n\nValue on reset: 0"]
359#[derive(Clone, Copy, Debug, PartialEq, Eq)]
360pub enum RESTART_MODE_A {
361    #[doc = "0: `0`"]
362    RESTART = 0,
363    #[doc = "1: `1`"]
364    STOP_RESTART = 1,
365}
366impl From<RESTART_MODE_A> for bool {
367    #[inline(always)]
368    fn from(variant: RESTART_MODE_A) -> Self {
369        variant as u8 != 0
370    }
371}
372impl RESTART_MODE_R {
373    #[doc = "Get enumerated values variant"]
374    #[inline(always)]
375    pub const fn variant(&self) -> RESTART_MODE_A {
376        match self.bits {
377            false => RESTART_MODE_A::RESTART,
378            true => RESTART_MODE_A::STOP_RESTART,
379        }
380    }
381    #[doc = "`0`"]
382    #[inline(always)]
383    pub fn is_restart(&self) -> bool {
384        *self == RESTART_MODE_A::RESTART
385    }
386    #[doc = "`1`"]
387    #[inline(always)]
388    pub fn is_stop_restart(&self) -> bool {
389        *self == RESTART_MODE_A::STOP_RESTART
390    }
391}
392#[doc = "Field `restart_mode` writer - Restart mode"]
393pub type RESTART_MODE_W<'a, REG> = crate::BitWriter<'a, REG, RESTART_MODE_A>;
394impl<'a, REG> RESTART_MODE_W<'a, REG>
395where
396    REG: crate::Writable + crate::RegisterSpec,
397{
398    #[doc = "`0`"]
399    #[inline(always)]
400    pub fn restart(self) -> &'a mut crate::W<REG> {
401        self.variant(RESTART_MODE_A::RESTART)
402    }
403    #[doc = "`1`"]
404    #[inline(always)]
405    pub fn stop_restart(self) -> &'a mut crate::W<REG> {
406        self.variant(RESTART_MODE_A::STOP_RESTART)
407    }
408}
409#[doc = "Field `start_tran` reader - Start transmission"]
410pub type START_TRAN_R = crate::BitReader<START_TRAN_A>;
411#[doc = "Start transmission\n\nValue on reset: 0"]
412#[derive(Clone, Copy, Debug, PartialEq, Eq)]
413pub enum START_TRAN_A {
414    #[doc = "0: `0`"]
415    IDLE = 0,
416    #[doc = "1: `1`"]
417    START = 1,
418}
419impl From<START_TRAN_A> for bool {
420    #[inline(always)]
421    fn from(variant: START_TRAN_A) -> Self {
422        variant as u8 != 0
423    }
424}
425impl START_TRAN_R {
426    #[doc = "Get enumerated values variant"]
427    #[inline(always)]
428    pub const fn variant(&self) -> START_TRAN_A {
429        match self.bits {
430            false => START_TRAN_A::IDLE,
431            true => START_TRAN_A::START,
432        }
433    }
434    #[doc = "`0`"]
435    #[inline(always)]
436    pub fn is_idle(&self) -> bool {
437        *self == START_TRAN_A::IDLE
438    }
439    #[doc = "`1`"]
440    #[inline(always)]
441    pub fn is_start(&self) -> bool {
442        *self == START_TRAN_A::START
443    }
444}
445#[doc = "Field `start_tran` writer - Start transmission"]
446pub type START_TRAN_W<'a, REG> = crate::BitWriter<'a, REG, START_TRAN_A>;
447impl<'a, REG> START_TRAN_W<'a, REG>
448where
449    REG: crate::Writable + crate::RegisterSpec,
450{
451    #[doc = "`0`"]
452    #[inline(always)]
453    pub fn idle(self) -> &'a mut crate::W<REG> {
454        self.variant(START_TRAN_A::IDLE)
455    }
456    #[doc = "`1`"]
457    #[inline(always)]
458    pub fn start(self) -> &'a mut crate::W<REG> {
459        self.variant(START_TRAN_A::START)
460    }
461}
462impl R {
463    #[doc = "Bit 0"]
464    #[inline(always)]
465    pub fn twi_drv_en(&self) -> TWI_DRV_EN_R {
466        TWI_DRV_EN_R::new((self.bits & 1) != 0)
467    }
468    #[doc = "Bit 1 - Software reset"]
469    #[inline(always)]
470    pub fn soft_reset(&self) -> SOFT_RESET_R {
471        SOFT_RESET_R::new(((self.bits >> 1) & 1) != 0)
472    }
473    #[doc = "Bits 8:15 - Timeout number"]
474    #[inline(always)]
475    pub fn timeout_n(&self) -> TIMEOUT_N_R {
476        TIMEOUT_N_R::new(((self.bits >> 8) & 0xff) as u8)
477    }
478    #[doc = "Bits 16:23 - TWI status"]
479    #[inline(always)]
480    pub fn twi_sta(&self) -> TWI_STA_R {
481        TWI_STA_R::new(((self.bits >> 16) & 0xff) as u8)
482    }
483    #[doc = "Bits 24:27 - Transition result"]
484    #[inline(always)]
485    pub fn tran_result(&self) -> TRAN_RESULT_R {
486        TRAN_RESULT_R::new(((self.bits >> 24) & 0x0f) as u8)
487    }
488    #[doc = "Bit 28 - Read transition mode"]
489    #[inline(always)]
490    pub fn read_tran_mode(&self) -> READ_TRAN_MODE_R {
491        READ_TRAN_MODE_R::new(((self.bits >> 28) & 1) != 0)
492    }
493    #[doc = "Bit 29 - Restart mode"]
494    #[inline(always)]
495    pub fn restart_mode(&self) -> RESTART_MODE_R {
496        RESTART_MODE_R::new(((self.bits >> 29) & 1) != 0)
497    }
498    #[doc = "Bit 31 - Start transmission"]
499    #[inline(always)]
500    pub fn start_tran(&self) -> START_TRAN_R {
501        START_TRAN_R::new(((self.bits >> 31) & 1) != 0)
502    }
503}
504impl W {
505    #[doc = "Bit 0"]
506    #[inline(always)]
507    #[must_use]
508    pub fn twi_drv_en(&mut self) -> TWI_DRV_EN_W<TWI_DRV_CTRL_SPEC> {
509        TWI_DRV_EN_W::new(self, 0)
510    }
511    #[doc = "Bit 1 - Software reset"]
512    #[inline(always)]
513    #[must_use]
514    pub fn soft_reset(&mut self) -> SOFT_RESET_W<TWI_DRV_CTRL_SPEC> {
515        SOFT_RESET_W::new(self, 1)
516    }
517    #[doc = "Bits 8:15 - Timeout number"]
518    #[inline(always)]
519    #[must_use]
520    pub fn timeout_n(&mut self) -> TIMEOUT_N_W<TWI_DRV_CTRL_SPEC> {
521        TIMEOUT_N_W::new(self, 8)
522    }
523    #[doc = "Bits 24:27 - Transition result"]
524    #[inline(always)]
525    #[must_use]
526    pub fn tran_result(&mut self) -> TRAN_RESULT_W<TWI_DRV_CTRL_SPEC> {
527        TRAN_RESULT_W::new(self, 24)
528    }
529    #[doc = "Bit 28 - Read transition mode"]
530    #[inline(always)]
531    #[must_use]
532    pub fn read_tran_mode(&mut self) -> READ_TRAN_MODE_W<TWI_DRV_CTRL_SPEC> {
533        READ_TRAN_MODE_W::new(self, 28)
534    }
535    #[doc = "Bit 29 - Restart mode"]
536    #[inline(always)]
537    #[must_use]
538    pub fn restart_mode(&mut self) -> RESTART_MODE_W<TWI_DRV_CTRL_SPEC> {
539        RESTART_MODE_W::new(self, 29)
540    }
541    #[doc = "Bit 31 - Start transmission"]
542    #[inline(always)]
543    #[must_use]
544    pub fn start_tran(&mut self) -> START_TRAN_W<TWI_DRV_CTRL_SPEC> {
545        START_TRAN_W::new(self, 31)
546    }
547    #[doc = r" Writes raw bits to the register."]
548    #[doc = r""]
549    #[doc = r" # Safety"]
550    #[doc = r""]
551    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
552    #[inline(always)]
553    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
554        self.bits = bits;
555        self
556    }
557}
558#[doc = "TWI_DRV Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_drv_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_drv_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
559pub struct TWI_DRV_CTRL_SPEC;
560impl crate::RegisterSpec for TWI_DRV_CTRL_SPEC {
561    type Ux = u32;
562}
563#[doc = "`read()` method returns [`twi_drv_ctrl::R`](R) reader structure"]
564impl crate::Readable for TWI_DRV_CTRL_SPEC {}
565#[doc = "`write(|w| ..)` method takes [`twi_drv_ctrl::W`](W) writer structure"]
566impl crate::Writable for TWI_DRV_CTRL_SPEC {
567    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
568    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
569}
570#[doc = "`reset()` method sets twi_drv_ctrl to value 0"]
571impl crate::Resettable for TWI_DRV_CTRL_SPEC {
572    const RESET_VALUE: Self::Ux = 0;
573}
d1_pac/twi/twi_drv_ctrl.rs

d1_pac/twi/
twi_drv_ctrl.rs
