d1_pac/twi/
twi_drv_bus_ctrl.rs

1#[doc = "Register `twi_drv_bus_ctrl` reader"]
2pub type R = crate::R<TWI_DRV_BUS_CTRL_SPEC>;
3#[doc = "Register `twi_drv_bus_ctrl` writer"]
4pub type W = crate::W<TWI_DRV_BUS_CTRL_SPEC>;
5#[doc = "Field `sda_moe` reader - SDA manual output enable"]
6pub type SDA_MOE_R = crate::BitReader;
7#[doc = "Field `sda_moe` writer - SDA manual output enable"]
8pub type SDA_MOE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `scl_moe` reader - SCL manual output enable"]
10pub type SCL_MOE_R = crate::BitReader;
11#[doc = "Field `scl_moe` writer - SCL manual output enable"]
12pub type SCL_MOE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `sda_mov` reader - SDA manual output value"]
14pub type SDA_MOV_R = crate::BitReader;
15#[doc = "Field `sda_mov` writer - SDA manual output value"]
16pub type SDA_MOV_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `scl_mov` reader - SCL manual output value"]
18pub type SCL_MOV_R = crate::BitReader;
19#[doc = "Field `scl_mov` writer - SCL manual output value"]
20pub type SCL_MOV_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `sda_sta` reader - SDA current status"]
22pub type SDA_STA_R = crate::BitReader;
23#[doc = "Field `scl_sta` reader - SCL current status"]
24pub type SCL_STA_R = crate::BitReader;
25#[doc = "Field `clk_m` reader - "]
26pub type CLK_M_R = crate::FieldReader;
27#[doc = "Field `clk_m` writer - "]
28pub type CLK_M_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29#[doc = "Field `clk_n` reader - "]
30pub type CLK_N_R = crate::FieldReader;
31#[doc = "Field `clk_n` writer - "]
32pub type CLK_N_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
33#[doc = "Field `clk_duty` reader - Setting duty cycle of clock as master"]
34pub type CLK_DUTY_R = crate::BitReader<CLK_DUTY_A>;
35#[doc = "Setting duty cycle of clock as master\n\nValue on reset: 0"]
36#[derive(Clone, Copy, Debug, PartialEq, Eq)]
37pub enum CLK_DUTY_A {
38    #[doc = "0: 50%"]
39    P50 = 0,
40    #[doc = "1: 40%"]
41    P40 = 1,
42}
43impl From<CLK_DUTY_A> for bool {
44    #[inline(always)]
45    fn from(variant: CLK_DUTY_A) -> Self {
46        variant as u8 != 0
47    }
48}
49impl CLK_DUTY_R {
50    #[doc = "Get enumerated values variant"]
51    #[inline(always)]
52    pub const fn variant(&self) -> CLK_DUTY_A {
53        match self.bits {
54            false => CLK_DUTY_A::P50,
55            true => CLK_DUTY_A::P40,
56        }
57    }
58    #[doc = "50%"]
59    #[inline(always)]
60    pub fn is_p50(&self) -> bool {
61        *self == CLK_DUTY_A::P50
62    }
63    #[doc = "40%"]
64    #[inline(always)]
65    pub fn is_p40(&self) -> bool {
66        *self == CLK_DUTY_A::P40
67    }
68}
69#[doc = "Field `clk_duty` writer - Setting duty cycle of clock as master"]
70pub type CLK_DUTY_W<'a, REG> = crate::BitWriter<'a, REG, CLK_DUTY_A>;
71impl<'a, REG> CLK_DUTY_W<'a, REG>
72where
73    REG: crate::Writable + crate::RegisterSpec,
74{
75    #[doc = "50%"]
76    #[inline(always)]
77    pub fn p50(self) -> &'a mut crate::W<REG> {
78        self.variant(CLK_DUTY_A::P50)
79    }
80    #[doc = "40%"]
81    #[inline(always)]
82    pub fn p40(self) -> &'a mut crate::W<REG> {
83        self.variant(CLK_DUTY_A::P40)
84    }
85}
86#[doc = "\n\nValue on reset: 0"]
87#[derive(Clone, Copy, Debug, PartialEq, Eq)]
88pub enum CLK_COUNT_MODE_AW {
89    #[doc = "0: scl clock high period count on oscl"]
90    OSCL = 0,
91    #[doc = "1: scl clock high period count on iscl"]
92    ISCL = 1,
93}
94impl From<CLK_COUNT_MODE_AW> for bool {
95    #[inline(always)]
96    fn from(variant: CLK_COUNT_MODE_AW) -> Self {
97        variant as u8 != 0
98    }
99}
100#[doc = "Field `clk_count_mode` writer - "]
101pub type CLK_COUNT_MODE_W<'a, REG> = crate::BitWriter<'a, REG, CLK_COUNT_MODE_AW>;
102impl<'a, REG> CLK_COUNT_MODE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    #[doc = "scl clock high period count on oscl"]
107    #[inline(always)]
108    pub fn oscl(self) -> &'a mut crate::W<REG> {
109        self.variant(CLK_COUNT_MODE_AW::OSCL)
110    }
111    #[doc = "scl clock high period count on iscl"]
112    #[inline(always)]
113    pub fn iscl(self) -> &'a mut crate::W<REG> {
114        self.variant(CLK_COUNT_MODE_AW::ISCL)
115    }
116}
117impl R {
118    #[doc = "Bit 0 - SDA manual output enable"]
119    #[inline(always)]
120    pub fn sda_moe(&self) -> SDA_MOE_R {
121        SDA_MOE_R::new((self.bits & 1) != 0)
122    }
123    #[doc = "Bit 1 - SCL manual output enable"]
124    #[inline(always)]
125    pub fn scl_moe(&self) -> SCL_MOE_R {
126        SCL_MOE_R::new(((self.bits >> 1) & 1) != 0)
127    }
128    #[doc = "Bit 2 - SDA manual output value"]
129    #[inline(always)]
130    pub fn sda_mov(&self) -> SDA_MOV_R {
131        SDA_MOV_R::new(((self.bits >> 2) & 1) != 0)
132    }
133    #[doc = "Bit 3 - SCL manual output value"]
134    #[inline(always)]
135    pub fn scl_mov(&self) -> SCL_MOV_R {
136        SCL_MOV_R::new(((self.bits >> 3) & 1) != 0)
137    }
138    #[doc = "Bit 6 - SDA current status"]
139    #[inline(always)]
140    pub fn sda_sta(&self) -> SDA_STA_R {
141        SDA_STA_R::new(((self.bits >> 6) & 1) != 0)
142    }
143    #[doc = "Bit 7 - SCL current status"]
144    #[inline(always)]
145    pub fn scl_sta(&self) -> SCL_STA_R {
146        SCL_STA_R::new(((self.bits >> 7) & 1) != 0)
147    }
148    #[doc = "Bits 8:11"]
149    #[inline(always)]
150    pub fn clk_m(&self) -> CLK_M_R {
151        CLK_M_R::new(((self.bits >> 8) & 0x0f) as u8)
152    }
153    #[doc = "Bits 12:14"]
154    #[inline(always)]
155    pub fn clk_n(&self) -> CLK_N_R {
156        CLK_N_R::new(((self.bits >> 12) & 7) as u8)
157    }
158    #[doc = "Bit 15 - Setting duty cycle of clock as master"]
159    #[inline(always)]
160    pub fn clk_duty(&self) -> CLK_DUTY_R {
161        CLK_DUTY_R::new(((self.bits >> 15) & 1) != 0)
162    }
163}
164impl W {
165    #[doc = "Bit 0 - SDA manual output enable"]
166    #[inline(always)]
167    #[must_use]
168    pub fn sda_moe(&mut self) -> SDA_MOE_W<TWI_DRV_BUS_CTRL_SPEC> {
169        SDA_MOE_W::new(self, 0)
170    }
171    #[doc = "Bit 1 - SCL manual output enable"]
172    #[inline(always)]
173    #[must_use]
174    pub fn scl_moe(&mut self) -> SCL_MOE_W<TWI_DRV_BUS_CTRL_SPEC> {
175        SCL_MOE_W::new(self, 1)
176    }
177    #[doc = "Bit 2 - SDA manual output value"]
178    #[inline(always)]
179    #[must_use]
180    pub fn sda_mov(&mut self) -> SDA_MOV_W<TWI_DRV_BUS_CTRL_SPEC> {
181        SDA_MOV_W::new(self, 2)
182    }
183    #[doc = "Bit 3 - SCL manual output value"]
184    #[inline(always)]
185    #[must_use]
186    pub fn scl_mov(&mut self) -> SCL_MOV_W<TWI_DRV_BUS_CTRL_SPEC> {
187        SCL_MOV_W::new(self, 3)
188    }
189    #[doc = "Bits 8:11"]
190    #[inline(always)]
191    #[must_use]
192    pub fn clk_m(&mut self) -> CLK_M_W<TWI_DRV_BUS_CTRL_SPEC> {
193        CLK_M_W::new(self, 8)
194    }
195    #[doc = "Bits 12:14"]
196    #[inline(always)]
197    #[must_use]
198    pub fn clk_n(&mut self) -> CLK_N_W<TWI_DRV_BUS_CTRL_SPEC> {
199        CLK_N_W::new(self, 12)
200    }
201    #[doc = "Bit 15 - Setting duty cycle of clock as master"]
202    #[inline(always)]
203    #[must_use]
204    pub fn clk_duty(&mut self) -> CLK_DUTY_W<TWI_DRV_BUS_CTRL_SPEC> {
205        CLK_DUTY_W::new(self, 15)
206    }
207    #[doc = "Bit 16"]
208    #[inline(always)]
209    #[must_use]
210    pub fn clk_count_mode(&mut self) -> CLK_COUNT_MODE_W<TWI_DRV_BUS_CTRL_SPEC> {
211        CLK_COUNT_MODE_W::new(self, 16)
212    }
213    #[doc = r" Writes raw bits to the register."]
214    #[doc = r""]
215    #[doc = r" # Safety"]
216    #[doc = r""]
217    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
218    #[inline(always)]
219    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
220        self.bits = bits;
221        self
222    }
223}
224#[doc = "TWI_DRV Bus Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_drv_bus_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_drv_bus_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
225pub struct TWI_DRV_BUS_CTRL_SPEC;
226impl crate::RegisterSpec for TWI_DRV_BUS_CTRL_SPEC {
227    type Ux = u32;
228}
229#[doc = "`read()` method returns [`twi_drv_bus_ctrl::R`](R) reader structure"]
230impl crate::Readable for TWI_DRV_BUS_CTRL_SPEC {}
231#[doc = "`write(|w| ..)` method takes [`twi_drv_bus_ctrl::W`](W) writer structure"]
232impl crate::Writable for TWI_DRV_BUS_CTRL_SPEC {
233    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
234    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
235}
236#[doc = "`reset()` method sets twi_drv_bus_ctrl to value 0"]
237impl crate::Resettable for TWI_DRV_BUS_CTRL_SPEC {
238    const RESET_VALUE: Self::Ux = 0;
239}
d1_pac/twi/twi_drv_bus_ctrl.rs

d1_pac/twi/
twi_drv_bus_ctrl.rs
