d1_pac/twi/
twi_cntr.rs

1#[doc = "Register `twi_cntr` reader"]
2pub type R = crate::R<TWI_CNTR_SPEC>;
3#[doc = "Register `twi_cntr` writer"]
4pub type W = crate::W<TWI_CNTR_SPEC>;
5#[doc = "Field `clk_count_mode` reader - "]
6pub type CLK_COUNT_MODE_R = crate::BitReader<CLK_COUNT_MODE_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CLK_COUNT_MODE_A {
10    #[doc = "0: scl clock high period count on oscl"]
11    OSCL = 0,
12    #[doc = "1: scl clock high period count on iscl"]
13    ISCL = 1,
14}
15impl From<CLK_COUNT_MODE_A> for bool {
16    #[inline(always)]
17    fn from(variant: CLK_COUNT_MODE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CLK_COUNT_MODE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CLK_COUNT_MODE_A {
25        match self.bits {
26            false => CLK_COUNT_MODE_A::OSCL,
27            true => CLK_COUNT_MODE_A::ISCL,
28        }
29    }
30    #[doc = "scl clock high period count on oscl"]
31    #[inline(always)]
32    pub fn is_oscl(&self) -> bool {
33        *self == CLK_COUNT_MODE_A::OSCL
34    }
35    #[doc = "scl clock high period count on iscl"]
36    #[inline(always)]
37    pub fn is_iscl(&self) -> bool {
38        *self == CLK_COUNT_MODE_A::ISCL
39    }
40}
41#[doc = "Field `clk_count_mode` writer - "]
42pub type CLK_COUNT_MODE_W<'a, REG> = crate::BitWriter<'a, REG, CLK_COUNT_MODE_A>;
43impl<'a, REG> CLK_COUNT_MODE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "scl clock high period count on oscl"]
48    #[inline(always)]
49    pub fn oscl(self) -> &'a mut crate::W<REG> {
50        self.variant(CLK_COUNT_MODE_A::OSCL)
51    }
52    #[doc = "scl clock high period count on iscl"]
53    #[inline(always)]
54    pub fn iscl(self) -> &'a mut crate::W<REG> {
55        self.variant(CLK_COUNT_MODE_A::ISCL)
56    }
57}
58#[doc = "Field `a_ack` reader - Assert Acknowledge"]
59pub type A_ACK_R = crate::BitReader;
60#[doc = "Field `a_ack` writer - Assert Acknowledge"]
61pub type A_ACK_W<'a, REG> = crate::BitWriter<'a, REG>;
62#[doc = "Field `int_flag` reader - Interrupt Flag"]
63pub type INT_FLAG_R = crate::BitReader;
64#[doc = "Field `int_flag` writer - Interrupt Flag"]
65pub type INT_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
66#[doc = "Field `m_stp` reader - Master Mode Stop"]
67pub type M_STP_R = crate::BitReader;
68#[doc = "Field `m_stp` writer - Master Mode Stop"]
69pub type M_STP_W<'a, REG> = crate::BitWriter<'a, REG>;
70#[doc = "Field `m_sta` reader - Master Mode Start"]
71pub type M_STA_R = crate::BitReader;
72#[doc = "Field `m_sta` writer - Master Mode Start"]
73pub type M_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
74#[doc = "Field `bus_en` reader - TWI Bus Enable"]
75pub type BUS_EN_R = crate::BitReader<BUS_EN_A>;
76#[doc = "TWI Bus Enable\n\nValue on reset: 0"]
77#[derive(Clone, Copy, Debug, PartialEq, Eq)]
78pub enum BUS_EN_A {
79    #[doc = "0: `0`"]
80    IGNORED = 0,
81    #[doc = "1: `1`"]
82    RESPOND = 1,
83}
84impl From<BUS_EN_A> for bool {
85    #[inline(always)]
86    fn from(variant: BUS_EN_A) -> Self {
87        variant as u8 != 0
88    }
89}
90impl BUS_EN_R {
91    #[doc = "Get enumerated values variant"]
92    #[inline(always)]
93    pub const fn variant(&self) -> BUS_EN_A {
94        match self.bits {
95            false => BUS_EN_A::IGNORED,
96            true => BUS_EN_A::RESPOND,
97        }
98    }
99    #[doc = "`0`"]
100    #[inline(always)]
101    pub fn is_ignored(&self) -> bool {
102        *self == BUS_EN_A::IGNORED
103    }
104    #[doc = "`1`"]
105    #[inline(always)]
106    pub fn is_respond(&self) -> bool {
107        *self == BUS_EN_A::RESPOND
108    }
109}
110#[doc = "Field `bus_en` writer - TWI Bus Enable"]
111pub type BUS_EN_W<'a, REG> = crate::BitWriter<'a, REG, BUS_EN_A>;
112impl<'a, REG> BUS_EN_W<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115{
116    #[doc = "`0`"]
117    #[inline(always)]
118    pub fn ignored(self) -> &'a mut crate::W<REG> {
119        self.variant(BUS_EN_A::IGNORED)
120    }
121    #[doc = "`1`"]
122    #[inline(always)]
123    pub fn respond(self) -> &'a mut crate::W<REG> {
124        self.variant(BUS_EN_A::RESPOND)
125    }
126}
127#[doc = "Field `int_en` reader - Interrupt Enable"]
128pub type INT_EN_R = crate::BitReader<INT_EN_A>;
129#[doc = "Interrupt Enable\n\nValue on reset: 0"]
130#[derive(Clone, Copy, Debug, PartialEq, Eq)]
131pub enum INT_EN_A {
132    #[doc = "0: The interrupt line always low"]
133    LOW = 0,
134    #[doc = "1: The interrupt line will go high when INT_FLAG is set"]
135    HIGH = 1,
136}
137impl From<INT_EN_A> for bool {
138    #[inline(always)]
139    fn from(variant: INT_EN_A) -> Self {
140        variant as u8 != 0
141    }
142}
143impl INT_EN_R {
144    #[doc = "Get enumerated values variant"]
145    #[inline(always)]
146    pub const fn variant(&self) -> INT_EN_A {
147        match self.bits {
148            false => INT_EN_A::LOW,
149            true => INT_EN_A::HIGH,
150        }
151    }
152    #[doc = "The interrupt line always low"]
153    #[inline(always)]
154    pub fn is_low(&self) -> bool {
155        *self == INT_EN_A::LOW
156    }
157    #[doc = "The interrupt line will go high when INT_FLAG is set"]
158    #[inline(always)]
159    pub fn is_high(&self) -> bool {
160        *self == INT_EN_A::HIGH
161    }
162}
163#[doc = "Field `int_en` writer - Interrupt Enable"]
164pub type INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, INT_EN_A>;
165impl<'a, REG> INT_EN_W<'a, REG>
166where
167    REG: crate::Writable + crate::RegisterSpec,
168{
169    #[doc = "The interrupt line always low"]
170    #[inline(always)]
171    pub fn low(self) -> &'a mut crate::W<REG> {
172        self.variant(INT_EN_A::LOW)
173    }
174    #[doc = "The interrupt line will go high when INT_FLAG is set"]
175    #[inline(always)]
176    pub fn high(self) -> &'a mut crate::W<REG> {
177        self.variant(INT_EN_A::HIGH)
178    }
179}
180impl R {
181    #[doc = "Bit 0"]
182    #[inline(always)]
183    pub fn clk_count_mode(&self) -> CLK_COUNT_MODE_R {
184        CLK_COUNT_MODE_R::new((self.bits & 1) != 0)
185    }
186    #[doc = "Bit 2 - Assert Acknowledge"]
187    #[inline(always)]
188    pub fn a_ack(&self) -> A_ACK_R {
189        A_ACK_R::new(((self.bits >> 2) & 1) != 0)
190    }
191    #[doc = "Bit 3 - Interrupt Flag"]
192    #[inline(always)]
193    pub fn int_flag(&self) -> INT_FLAG_R {
194        INT_FLAG_R::new(((self.bits >> 3) & 1) != 0)
195    }
196    #[doc = "Bit 4 - Master Mode Stop"]
197    #[inline(always)]
198    pub fn m_stp(&self) -> M_STP_R {
199        M_STP_R::new(((self.bits >> 4) & 1) != 0)
200    }
201    #[doc = "Bit 5 - Master Mode Start"]
202    #[inline(always)]
203    pub fn m_sta(&self) -> M_STA_R {
204        M_STA_R::new(((self.bits >> 5) & 1) != 0)
205    }
206    #[doc = "Bit 6 - TWI Bus Enable"]
207    #[inline(always)]
208    pub fn bus_en(&self) -> BUS_EN_R {
209        BUS_EN_R::new(((self.bits >> 6) & 1) != 0)
210    }
211    #[doc = "Bit 7 - Interrupt Enable"]
212    #[inline(always)]
213    pub fn int_en(&self) -> INT_EN_R {
214        INT_EN_R::new(((self.bits >> 7) & 1) != 0)
215    }
216}
217impl W {
218    #[doc = "Bit 0"]
219    #[inline(always)]
220    #[must_use]
221    pub fn clk_count_mode(&mut self) -> CLK_COUNT_MODE_W<TWI_CNTR_SPEC> {
222        CLK_COUNT_MODE_W::new(self, 0)
223    }
224    #[doc = "Bit 2 - Assert Acknowledge"]
225    #[inline(always)]
226    #[must_use]
227    pub fn a_ack(&mut self) -> A_ACK_W<TWI_CNTR_SPEC> {
228        A_ACK_W::new(self, 2)
229    }
230    #[doc = "Bit 3 - Interrupt Flag"]
231    #[inline(always)]
232    #[must_use]
233    pub fn int_flag(&mut self) -> INT_FLAG_W<TWI_CNTR_SPEC> {
234        INT_FLAG_W::new(self, 3)
235    }
236    #[doc = "Bit 4 - Master Mode Stop"]
237    #[inline(always)]
238    #[must_use]
239    pub fn m_stp(&mut self) -> M_STP_W<TWI_CNTR_SPEC> {
240        M_STP_W::new(self, 4)
241    }
242    #[doc = "Bit 5 - Master Mode Start"]
243    #[inline(always)]
244    #[must_use]
245    pub fn m_sta(&mut self) -> M_STA_W<TWI_CNTR_SPEC> {
246        M_STA_W::new(self, 5)
247    }
248    #[doc = "Bit 6 - TWI Bus Enable"]
249    #[inline(always)]
250    #[must_use]
251    pub fn bus_en(&mut self) -> BUS_EN_W<TWI_CNTR_SPEC> {
252        BUS_EN_W::new(self, 6)
253    }
254    #[doc = "Bit 7 - Interrupt Enable"]
255    #[inline(always)]
256    #[must_use]
257    pub fn int_en(&mut self) -> INT_EN_W<TWI_CNTR_SPEC> {
258        INT_EN_W::new(self, 7)
259    }
260    #[doc = r" Writes raw bits to the register."]
261    #[doc = r""]
262    #[doc = r" # Safety"]
263    #[doc = r""]
264    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
265    #[inline(always)]
266    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
267        self.bits = bits;
268        self
269    }
270}
271#[doc = "TWI Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_cntr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_cntr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
272pub struct TWI_CNTR_SPEC;
273impl crate::RegisterSpec for TWI_CNTR_SPEC {
274    type Ux = u32;
275}
276#[doc = "`read()` method returns [`twi_cntr::R`](R) reader structure"]
277impl crate::Readable for TWI_CNTR_SPEC {}
278#[doc = "`write(|w| ..)` method takes [`twi_cntr::W`](W) writer structure"]
279impl crate::Writable for TWI_CNTR_SPEC {
280    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
281    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
282}
283#[doc = "`reset()` method sets twi_cntr to value 0"]
284impl crate::Resettable for TWI_CNTR_SPEC {
285    const RESET_VALUE: Self::Ux = 0;
286}
d1_pac/twi/twi_cntr.rs

d1_pac/twi/
twi_cntr.rs
