d1_pac/twi/
twi_ccr.rs

1#[doc = "Register `twi_ccr` reader"]
2pub type R = crate::R<TWI_CCR_SPEC>;
3#[doc = "Register `twi_ccr` writer"]
4pub type W = crate::W<TWI_CCR_SPEC>;
5#[doc = "Field `clk_n` reader - "]
6pub type CLK_N_R = crate::FieldReader;
7#[doc = "Field `clk_n` writer - "]
8pub type CLK_N_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `clk_m` reader - "]
10pub type CLK_M_R = crate::FieldReader;
11#[doc = "Field `clk_m` writer - "]
12pub type CLK_M_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `clk_duty` reader - Setting duty cycle of clock as master"]
14pub type CLK_DUTY_R = crate::BitReader<CLK_DUTY_A>;
15#[doc = "Setting duty cycle of clock as master\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17pub enum CLK_DUTY_A {
18    #[doc = "0: 50%"]
19    P50 = 0,
20    #[doc = "1: 40%"]
21    P40 = 1,
22}
23impl From<CLK_DUTY_A> for bool {
24    #[inline(always)]
25    fn from(variant: CLK_DUTY_A) -> Self {
26        variant as u8 != 0
27    }
28}
29impl CLK_DUTY_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> CLK_DUTY_A {
33        match self.bits {
34            false => CLK_DUTY_A::P50,
35            true => CLK_DUTY_A::P40,
36        }
37    }
38    #[doc = "50%"]
39    #[inline(always)]
40    pub fn is_p50(&self) -> bool {
41        *self == CLK_DUTY_A::P50
42    }
43    #[doc = "40%"]
44    #[inline(always)]
45    pub fn is_p40(&self) -> bool {
46        *self == CLK_DUTY_A::P40
47    }
48}
49#[doc = "Field `clk_duty` writer - Setting duty cycle of clock as master"]
50pub type CLK_DUTY_W<'a, REG> = crate::BitWriter<'a, REG, CLK_DUTY_A>;
51impl<'a, REG> CLK_DUTY_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "50%"]
56    #[inline(always)]
57    pub fn p50(self) -> &'a mut crate::W<REG> {
58        self.variant(CLK_DUTY_A::P50)
59    }
60    #[doc = "40%"]
61    #[inline(always)]
62    pub fn p40(self) -> &'a mut crate::W<REG> {
63        self.variant(CLK_DUTY_A::P40)
64    }
65}
66impl R {
67    #[doc = "Bits 0:2"]
68    #[inline(always)]
69    pub fn clk_n(&self) -> CLK_N_R {
70        CLK_N_R::new((self.bits & 7) as u8)
71    }
72    #[doc = "Bits 3:6"]
73    #[inline(always)]
74    pub fn clk_m(&self) -> CLK_M_R {
75        CLK_M_R::new(((self.bits >> 3) & 0x0f) as u8)
76    }
77    #[doc = "Bit 7 - Setting duty cycle of clock as master"]
78    #[inline(always)]
79    pub fn clk_duty(&self) -> CLK_DUTY_R {
80        CLK_DUTY_R::new(((self.bits >> 7) & 1) != 0)
81    }
82}
83impl W {
84    #[doc = "Bits 0:2"]
85    #[inline(always)]
86    #[must_use]
87    pub fn clk_n(&mut self) -> CLK_N_W<TWI_CCR_SPEC> {
88        CLK_N_W::new(self, 0)
89    }
90    #[doc = "Bits 3:6"]
91    #[inline(always)]
92    #[must_use]
93    pub fn clk_m(&mut self) -> CLK_M_W<TWI_CCR_SPEC> {
94        CLK_M_W::new(self, 3)
95    }
96    #[doc = "Bit 7 - Setting duty cycle of clock as master"]
97    #[inline(always)]
98    #[must_use]
99    pub fn clk_duty(&mut self) -> CLK_DUTY_W<TWI_CCR_SPEC> {
100        CLK_DUTY_W::new(self, 7)
101    }
102    #[doc = r" Writes raw bits to the register."]
103    #[doc = r""]
104    #[doc = r" # Safety"]
105    #[doc = r""]
106    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
107    #[inline(always)]
108    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
109        self.bits = bits;
110        self
111    }
112}
113#[doc = "TWI Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_ccr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
114pub struct TWI_CCR_SPEC;
115impl crate::RegisterSpec for TWI_CCR_SPEC {
116    type Ux = u32;
117}
118#[doc = "`read()` method returns [`twi_ccr::R`](R) reader structure"]
119impl crate::Readable for TWI_CCR_SPEC {}
120#[doc = "`write(|w| ..)` method takes [`twi_ccr::W`](W) writer structure"]
121impl crate::Writable for TWI_CCR_SPEC {
122    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
123    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
124}
125#[doc = "`reset()` method sets twi_ccr to value 0"]
126impl crate::Resettable for TWI_CCR_SPEC {
127    const RESET_VALUE: Self::Ux = 0;
128}
d1_pac/twi/twi_ccr.rs

d1_pac/twi/
twi_ccr.rs
