d1_pac/twi/
twi_addr.rs

1#[doc = "Register `twi_addr` reader"]
2pub type R = crate::R<TWI_ADDR_SPEC>;
3#[doc = "Register `twi_addr` writer"]
4pub type W = crate::W<TWI_ADDR_SPEC>;
5#[doc = "Field `gce` reader - "]
6pub type GCE_R = crate::BitReader<GCE_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum GCE_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<GCE_A> for bool {
16    #[inline(always)]
17    fn from(variant: GCE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl GCE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> GCE_A {
25        match self.bits {
26            false => GCE_A::DISABLE,
27            true => GCE_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == GCE_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == GCE_A::ENABLE
39    }
40}
41#[doc = "Field `gce` writer - "]
42pub type GCE_W<'a, REG> = crate::BitWriter<'a, REG, GCE_A>;
43impl<'a, REG> GCE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(GCE_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(GCE_A::ENABLE)
56    }
57}
58#[doc = "Field `sla` reader - Slave Address"]
59pub type SLA_R = crate::FieldReader;
60#[doc = "Field `sla` writer - Slave Address"]
61pub type SLA_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
62impl R {
63    #[doc = "Bit 0"]
64    #[inline(always)]
65    pub fn gce(&self) -> GCE_R {
66        GCE_R::new((self.bits & 1) != 0)
67    }
68    #[doc = "Bits 1:7 - Slave Address"]
69    #[inline(always)]
70    pub fn sla(&self) -> SLA_R {
71        SLA_R::new(((self.bits >> 1) & 0x7f) as u8)
72    }
73}
74impl W {
75    #[doc = "Bit 0"]
76    #[inline(always)]
77    #[must_use]
78    pub fn gce(&mut self) -> GCE_W<TWI_ADDR_SPEC> {
79        GCE_W::new(self, 0)
80    }
81    #[doc = "Bits 1:7 - Slave Address"]
82    #[inline(always)]
83    #[must_use]
84    pub fn sla(&mut self) -> SLA_W<TWI_ADDR_SPEC> {
85        SLA_W::new(self, 1)
86    }
87    #[doc = r" Writes raw bits to the register."]
88    #[doc = r""]
89    #[doc = r" # Safety"]
90    #[doc = r""]
91    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
92    #[inline(always)]
93    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
94        self.bits = bits;
95        self
96    }
97}
98#[doc = "TWI Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct TWI_ADDR_SPEC;
100impl crate::RegisterSpec for TWI_ADDR_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [`twi_addr::R`](R) reader structure"]
104impl crate::Readable for TWI_ADDR_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`twi_addr::W`](W) writer structure"]
106impl crate::Writable for TWI_ADDR_SPEC {
107    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
108    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
109}
110#[doc = "`reset()` method sets twi_addr to value 0"]
111impl crate::Resettable for TWI_ADDR_SPEC {
112    const RESET_VALUE: Self::Ux = 0;
113}
d1_pac/twi/twi_addr.rs

d1_pac/twi/
twi_addr.rs
