d1_pac/tve/
tve_hd_vsync.rs

1#[doc = "Register `tve_hd_vsync` reader"]
2pub type R = crate::R<TVE_HD_VSYNC_SPEC>;
3#[doc = "Register `tve_hd_vsync` writer"]
4pub type W = crate::W<TVE_HD_VSYNC_SPEC>;
5#[doc = "Field `front_porch_like_in_hd_mode_vsync` reader - "]
6pub type FRONT_PORCH_LIKE_IN_HD_MODE_VSYNC_R = crate::FieldReader<u16>;
7#[doc = "Field `front_porch_like_in_hd_mode_vsync` writer - "]
8pub type FRONT_PORCH_LIKE_IN_HD_MODE_VSYNC_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Field `broad_plus_cycle_number_in_hd_mode_vsync` reader - "]
10pub type BROAD_PLUS_CYCLE_NUMBER_IN_HD_MODE_VSYNC_R = crate::FieldReader<u16>;
11#[doc = "Field `broad_plus_cycle_number_in_hd_mode_vsync` writer - "]
12pub type BROAD_PLUS_CYCLE_NUMBER_IN_HD_MODE_VSYNC_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
13impl R {
14    #[doc = "Bits 0:11"]
15    #[inline(always)]
16    pub fn front_porch_like_in_hd_mode_vsync(&self) -> FRONT_PORCH_LIKE_IN_HD_MODE_VSYNC_R {
17        FRONT_PORCH_LIKE_IN_HD_MODE_VSYNC_R::new((self.bits & 0x0fff) as u16)
18    }
19    #[doc = "Bits 16:27"]
20    #[inline(always)]
21    pub fn broad_plus_cycle_number_in_hd_mode_vsync(
22        &self,
23    ) -> BROAD_PLUS_CYCLE_NUMBER_IN_HD_MODE_VSYNC_R {
24        BROAD_PLUS_CYCLE_NUMBER_IN_HD_MODE_VSYNC_R::new(((self.bits >> 16) & 0x0fff) as u16)
25    }
26}
27impl W {
28    #[doc = "Bits 0:11"]
29    #[inline(always)]
30    #[must_use]
31    pub fn front_porch_like_in_hd_mode_vsync(
32        &mut self,
33    ) -> FRONT_PORCH_LIKE_IN_HD_MODE_VSYNC_W<TVE_HD_VSYNC_SPEC> {
34        FRONT_PORCH_LIKE_IN_HD_MODE_VSYNC_W::new(self, 0)
35    }
36    #[doc = "Bits 16:27"]
37    #[inline(always)]
38    #[must_use]
39    pub fn broad_plus_cycle_number_in_hd_mode_vsync(
40        &mut self,
41    ) -> BROAD_PLUS_CYCLE_NUMBER_IN_HD_MODE_VSYNC_W<TVE_HD_VSYNC_SPEC> {
42        BROAD_PLUS_CYCLE_NUMBER_IN_HD_MODE_VSYNC_W::new(self, 16)
43    }
44    #[doc = r" Writes raw bits to the register."]
45    #[doc = r""]
46    #[doc = r" # Safety"]
47    #[doc = r""]
48    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
49    #[inline(always)]
50    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
51        self.bits = bits;
52        self
53    }
54}
55#[doc = "TV Encoder HD Mode VSYNC Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tve_hd_vsync::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tve_hd_vsync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
56pub struct TVE_HD_VSYNC_SPEC;
57impl crate::RegisterSpec for TVE_HD_VSYNC_SPEC {
58    type Ux = u32;
59}
60#[doc = "`read()` method returns [`tve_hd_vsync::R`](R) reader structure"]
61impl crate::Readable for TVE_HD_VSYNC_SPEC {}
62#[doc = "`write(|w| ..)` method takes [`tve_hd_vsync::W`](W) writer structure"]
63impl crate::Writable for TVE_HD_VSYNC_SPEC {
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
66}
67#[doc = "`reset()` method sets tve_hd_vsync to value 0x16"]
68impl crate::Resettable for TVE_HD_VSYNC_SPEC {
69    const RESET_VALUE: Self::Ux = 0x16;
70}
d1_pac/tve/tve_hd_vsync.rs

d1_pac/tve/
tve_hd_vsync.rs
