d1_pac/tve/
tve_clock_gating.rs

1#[doc = "Register `tve_clock_gating` reader"]
2pub type R = crate::R<TVE_CLOCK_GATING_SPEC>;
3#[doc = "Register `tve_clock_gating` writer"]
4pub type W = crate::W<TVE_CLOCK_GATING_SPEC>;
5#[doc = "Field `tve_en` reader - Video Encoder enable, default disable, write 1 to take it out of the reset state"]
6pub type TVE_EN_R = crate::BitReader<TVE_EN_A>;
7#[doc = "Video Encoder enable, default disable, write 1 to take it out of the reset state\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TVE_EN_A {
10    #[doc = "0: Disable"]
11    DISABLE = 0,
12    #[doc = "1: Enable"]
13    ENABLE = 1,
14}
15impl From<TVE_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: TVE_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TVE_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TVE_EN_A {
25        match self.bits {
26            false => TVE_EN_A::DISABLE,
27            true => TVE_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == TVE_EN_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == TVE_EN_A::ENABLE
39    }
40}
41#[doc = "Field `tve_en` writer - Video Encoder enable, default disable, write 1 to take it out of the reset state"]
42pub type TVE_EN_W<'a, REG> = crate::BitWriter<'a, REG, TVE_EN_A>;
43impl<'a, REG> TVE_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(TVE_EN_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(TVE_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `upsample_for_cvbs` reader - "]
59pub type UPSAMPLE_FOR_CVBS_R = crate::FieldReader<UPSAMPLE_FOR_CVBS_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u8)]
63pub enum UPSAMPLE_FOR_CVBS_A {
64    #[doc = "0: 27 MHz"]
65    F27M = 0,
66    #[doc = "1: 54 MHz"]
67    F54M = 1,
68    #[doc = "2: 108 MHz"]
69    F108M = 2,
70    #[doc = "3: 216 MHz"]
71    F216M = 3,
72}
73impl From<UPSAMPLE_FOR_CVBS_A> for u8 {
74    #[inline(always)]
75    fn from(variant: UPSAMPLE_FOR_CVBS_A) -> Self {
76        variant as _
77    }
78}
79impl crate::FieldSpec for UPSAMPLE_FOR_CVBS_A {
80    type Ux = u8;
81}
82impl UPSAMPLE_FOR_CVBS_R {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub const fn variant(&self) -> UPSAMPLE_FOR_CVBS_A {
86        match self.bits {
87            0 => UPSAMPLE_FOR_CVBS_A::F27M,
88            1 => UPSAMPLE_FOR_CVBS_A::F54M,
89            2 => UPSAMPLE_FOR_CVBS_A::F108M,
90            3 => UPSAMPLE_FOR_CVBS_A::F216M,
91            _ => unreachable!(),
92        }
93    }
94    #[doc = "27 MHz"]
95    #[inline(always)]
96    pub fn is_f27m(&self) -> bool {
97        *self == UPSAMPLE_FOR_CVBS_A::F27M
98    }
99    #[doc = "54 MHz"]
100    #[inline(always)]
101    pub fn is_f54m(&self) -> bool {
102        *self == UPSAMPLE_FOR_CVBS_A::F54M
103    }
104    #[doc = "108 MHz"]
105    #[inline(always)]
106    pub fn is_f108m(&self) -> bool {
107        *self == UPSAMPLE_FOR_CVBS_A::F108M
108    }
109    #[doc = "216 MHz"]
110    #[inline(always)]
111    pub fn is_f216m(&self) -> bool {
112        *self == UPSAMPLE_FOR_CVBS_A::F216M
113    }
114}
115#[doc = "Field `upsample_for_cvbs` writer - "]
116pub type UPSAMPLE_FOR_CVBS_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, UPSAMPLE_FOR_CVBS_A>;
117impl<'a, REG> UPSAMPLE_FOR_CVBS_W<'a, REG>
118where
119    REG: crate::Writable + crate::RegisterSpec,
120    REG::Ux: From<u8>,
121{
122    #[doc = "27 MHz"]
123    #[inline(always)]
124    pub fn f27m(self) -> &'a mut crate::W<REG> {
125        self.variant(UPSAMPLE_FOR_CVBS_A::F27M)
126    }
127    #[doc = "54 MHz"]
128    #[inline(always)]
129    pub fn f54m(self) -> &'a mut crate::W<REG> {
130        self.variant(UPSAMPLE_FOR_CVBS_A::F54M)
131    }
132    #[doc = "108 MHz"]
133    #[inline(always)]
134    pub fn f108m(self) -> &'a mut crate::W<REG> {
135        self.variant(UPSAMPLE_FOR_CVBS_A::F108M)
136    }
137    #[doc = "216 MHz"]
138    #[inline(always)]
139    pub fn f216m(self) -> &'a mut crate::W<REG> {
140        self.variant(UPSAMPLE_FOR_CVBS_A::F216M)
141    }
142}
143#[doc = "Field `upsample_for_ypbpr` reader - "]
144pub type UPSAMPLE_FOR_YPBPR_R = crate::BitReader<UPSAMPLE_FOR_YPBPR_A>;
145#[doc = "\n\nValue on reset: 0"]
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147pub enum UPSAMPLE_FOR_YPBPR_A {
148    #[doc = "0: 1x"]
149    X1 = 0,
150    #[doc = "1: 2x"]
151    X2 = 1,
152}
153impl From<UPSAMPLE_FOR_YPBPR_A> for bool {
154    #[inline(always)]
155    fn from(variant: UPSAMPLE_FOR_YPBPR_A) -> Self {
156        variant as u8 != 0
157    }
158}
159impl UPSAMPLE_FOR_YPBPR_R {
160    #[doc = "Get enumerated values variant"]
161    #[inline(always)]
162    pub const fn variant(&self) -> UPSAMPLE_FOR_YPBPR_A {
163        match self.bits {
164            false => UPSAMPLE_FOR_YPBPR_A::X1,
165            true => UPSAMPLE_FOR_YPBPR_A::X2,
166        }
167    }
168    #[doc = "1x"]
169    #[inline(always)]
170    pub fn is_x1(&self) -> bool {
171        *self == UPSAMPLE_FOR_YPBPR_A::X1
172    }
173    #[doc = "2x"]
174    #[inline(always)]
175    pub fn is_x2(&self) -> bool {
176        *self == UPSAMPLE_FOR_YPBPR_A::X2
177    }
178}
179#[doc = "Field `upsample_for_ypbpr` writer - "]
180pub type UPSAMPLE_FOR_YPBPR_W<'a, REG> = crate::BitWriter<'a, REG, UPSAMPLE_FOR_YPBPR_A>;
181impl<'a, REG> UPSAMPLE_FOR_YPBPR_W<'a, REG>
182where
183    REG: crate::Writable + crate::RegisterSpec,
184{
185    #[doc = "1x"]
186    #[inline(always)]
187    pub fn x1(self) -> &'a mut crate::W<REG> {
188        self.variant(UPSAMPLE_FOR_YPBPR_A::X1)
189    }
190    #[doc = "2x"]
191    #[inline(always)]
192    pub fn x2(self) -> &'a mut crate::W<REG> {
193        self.variant(UPSAMPLE_FOR_YPBPR_A::X2)
194    }
195}
196#[doc = "Field `bist_en` reader - "]
197pub type BIST_EN_R = crate::BitReader<BIST_EN_A>;
198#[doc = "\n\nValue on reset: 0"]
199#[derive(Clone, Copy, Debug, PartialEq, Eq)]
200pub enum BIST_EN_A {
201    #[doc = "0: Normal mode"]
202    NORMAL = 0,
203    #[doc = "1: Bist mode"]
204    B_IST = 1,
205}
206impl From<BIST_EN_A> for bool {
207    #[inline(always)]
208    fn from(variant: BIST_EN_A) -> Self {
209        variant as u8 != 0
210    }
211}
212impl BIST_EN_R {
213    #[doc = "Get enumerated values variant"]
214    #[inline(always)]
215    pub const fn variant(&self) -> BIST_EN_A {
216        match self.bits {
217            false => BIST_EN_A::NORMAL,
218            true => BIST_EN_A::B_IST,
219        }
220    }
221    #[doc = "Normal mode"]
222    #[inline(always)]
223    pub fn is_normal(&self) -> bool {
224        *self == BIST_EN_A::NORMAL
225    }
226    #[doc = "Bist mode"]
227    #[inline(always)]
228    pub fn is_b_ist(&self) -> bool {
229        *self == BIST_EN_A::B_IST
230    }
231}
232#[doc = "Field `bist_en` writer - "]
233pub type BIST_EN_W<'a, REG> = crate::BitWriter<'a, REG, BIST_EN_A>;
234impl<'a, REG> BIST_EN_W<'a, REG>
235where
236    REG: crate::Writable + crate::RegisterSpec,
237{
238    #[doc = "Normal mode"]
239    #[inline(always)]
240    pub fn normal(self) -> &'a mut crate::W<REG> {
241        self.variant(BIST_EN_A::NORMAL)
242    }
243    #[doc = "Bist mode"]
244    #[inline(always)]
245    pub fn b_ist(self) -> &'a mut crate::W<REG> {
246        self.variant(BIST_EN_A::B_IST)
247    }
248}
249#[doc = "Field `clock_gate_dis` reader - "]
250pub type CLOCK_GATE_DIS_R = crate::BitReader<CLOCK_GATE_DIS_A>;
251#[doc = "\n\nValue on reset: 0"]
252#[derive(Clone, Copy, Debug, PartialEq, Eq)]
253pub enum CLOCK_GATE_DIS_A {
254    #[doc = "0: Enable"]
255    ENABLE = 0,
256    #[doc = "1: Disable"]
257    DISABLE = 1,
258}
259impl From<CLOCK_GATE_DIS_A> for bool {
260    #[inline(always)]
261    fn from(variant: CLOCK_GATE_DIS_A) -> Self {
262        variant as u8 != 0
263    }
264}
265impl CLOCK_GATE_DIS_R {
266    #[doc = "Get enumerated values variant"]
267    #[inline(always)]
268    pub const fn variant(&self) -> CLOCK_GATE_DIS_A {
269        match self.bits {
270            false => CLOCK_GATE_DIS_A::ENABLE,
271            true => CLOCK_GATE_DIS_A::DISABLE,
272        }
273    }
274    #[doc = "Enable"]
275    #[inline(always)]
276    pub fn is_enable(&self) -> bool {
277        *self == CLOCK_GATE_DIS_A::ENABLE
278    }
279    #[doc = "Disable"]
280    #[inline(always)]
281    pub fn is_disable(&self) -> bool {
282        *self == CLOCK_GATE_DIS_A::DISABLE
283    }
284}
285#[doc = "Field `clock_gate_dis` writer - "]
286pub type CLOCK_GATE_DIS_W<'a, REG> = crate::BitWriter<'a, REG, CLOCK_GATE_DIS_A>;
287impl<'a, REG> CLOCK_GATE_DIS_W<'a, REG>
288where
289    REG: crate::Writable + crate::RegisterSpec,
290{
291    #[doc = "Enable"]
292    #[inline(always)]
293    pub fn enable(self) -> &'a mut crate::W<REG> {
294        self.variant(CLOCK_GATE_DIS_A::ENABLE)
295    }
296    #[doc = "Disable"]
297    #[inline(always)]
298    pub fn disable(self) -> &'a mut crate::W<REG> {
299        self.variant(CLOCK_GATE_DIS_A::DISABLE)
300    }
301}
302impl R {
303    #[doc = "Bit 0 - Video Encoder enable, default disable, write 1 to take it out of the reset state"]
304    #[inline(always)]
305    pub fn tve_en(&self) -> TVE_EN_R {
306        TVE_EN_R::new((self.bits & 1) != 0)
307    }
308    #[doc = "Bits 20:21"]
309    #[inline(always)]
310    pub fn upsample_for_cvbs(&self) -> UPSAMPLE_FOR_CVBS_R {
311        UPSAMPLE_FOR_CVBS_R::new(((self.bits >> 20) & 3) as u8)
312    }
313    #[doc = "Bit 22"]
314    #[inline(always)]
315    pub fn upsample_for_ypbpr(&self) -> UPSAMPLE_FOR_YPBPR_R {
316        UPSAMPLE_FOR_YPBPR_R::new(((self.bits >> 22) & 1) != 0)
317    }
318    #[doc = "Bit 28"]
319    #[inline(always)]
320    pub fn bist_en(&self) -> BIST_EN_R {
321        BIST_EN_R::new(((self.bits >> 28) & 1) != 0)
322    }
323    #[doc = "Bit 31"]
324    #[inline(always)]
325    pub fn clock_gate_dis(&self) -> CLOCK_GATE_DIS_R {
326        CLOCK_GATE_DIS_R::new(((self.bits >> 31) & 1) != 0)
327    }
328}
329impl W {
330    #[doc = "Bit 0 - Video Encoder enable, default disable, write 1 to take it out of the reset state"]
331    #[inline(always)]
332    #[must_use]
333    pub fn tve_en(&mut self) -> TVE_EN_W<TVE_CLOCK_GATING_SPEC> {
334        TVE_EN_W::new(self, 0)
335    }
336    #[doc = "Bits 20:21"]
337    #[inline(always)]
338    #[must_use]
339    pub fn upsample_for_cvbs(&mut self) -> UPSAMPLE_FOR_CVBS_W<TVE_CLOCK_GATING_SPEC> {
340        UPSAMPLE_FOR_CVBS_W::new(self, 20)
341    }
342    #[doc = "Bit 22"]
343    #[inline(always)]
344    #[must_use]
345    pub fn upsample_for_ypbpr(&mut self) -> UPSAMPLE_FOR_YPBPR_W<TVE_CLOCK_GATING_SPEC> {
346        UPSAMPLE_FOR_YPBPR_W::new(self, 22)
347    }
348    #[doc = "Bit 28"]
349    #[inline(always)]
350    #[must_use]
351    pub fn bist_en(&mut self) -> BIST_EN_W<TVE_CLOCK_GATING_SPEC> {
352        BIST_EN_W::new(self, 28)
353    }
354    #[doc = "Bit 31"]
355    #[inline(always)]
356    #[must_use]
357    pub fn clock_gate_dis(&mut self) -> CLOCK_GATE_DIS_W<TVE_CLOCK_GATING_SPEC> {
358        CLOCK_GATE_DIS_W::new(self, 31)
359    }
360    #[doc = r" Writes raw bits to the register."]
361    #[doc = r""]
362    #[doc = r" # Safety"]
363    #[doc = r""]
364    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
365    #[inline(always)]
366    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
367        self.bits = bits;
368        self
369    }
370}
371#[doc = "TV Encoder Clock Gating Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tve_clock_gating::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tve_clock_gating::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
372pub struct TVE_CLOCK_GATING_SPEC;
373impl crate::RegisterSpec for TVE_CLOCK_GATING_SPEC {
374    type Ux = u32;
375}
376#[doc = "`read()` method returns [`tve_clock_gating::R`](R) reader structure"]
377impl crate::Readable for TVE_CLOCK_GATING_SPEC {}
378#[doc = "`write(|w| ..)` method takes [`tve_clock_gating::W`](W) writer structure"]
379impl crate::Writable for TVE_CLOCK_GATING_SPEC {
380    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
381    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
382}
383#[doc = "`reset()` method sets tve_clock_gating to value 0"]
384impl crate::Resettable for TVE_CLOCK_GATING_SPEC {
385    const RESET_VALUE: Self::Ux = 0;
386}
d1_pac/tve/tve_clock_gating.rs

d1_pac/tve/
tve_clock_gating.rs
