d1_pac/tpadc/
tp_int_fifo_ctrl.rs

1#[doc = "Register `tp_int_fifo_ctrl` reader"]
2pub type R = crate::R<TP_INT_FIFO_CTRL_SPEC>;
3#[doc = "Register `tp_int_fifo_ctrl` writer"]
4pub type W = crate::W<TP_INT_FIFO_CTRL_SPEC>;
5#[doc = "Field `tp_down_irq_en` reader - TP First Touch (Stylus DOWN) IRQ Enable"]
6pub type TP_DOWN_IRQ_EN_R = crate::BitReader<TP_DOWN_IRQ_EN_A>;
7#[doc = "TP First Touch (Stylus DOWN) IRQ Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TP_DOWN_IRQ_EN_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<TP_DOWN_IRQ_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: TP_DOWN_IRQ_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TP_DOWN_IRQ_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TP_DOWN_IRQ_EN_A {
25        match self.bits {
26            false => TP_DOWN_IRQ_EN_A::DISABLE,
27            true => TP_DOWN_IRQ_EN_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == TP_DOWN_IRQ_EN_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == TP_DOWN_IRQ_EN_A::ENABLE
39    }
40}
41#[doc = "Field `tp_down_irq_en` writer - TP First Touch (Stylus DOWN) IRQ Enable"]
42pub type TP_DOWN_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, TP_DOWN_IRQ_EN_A>;
43impl<'a, REG> TP_DOWN_IRQ_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(TP_DOWN_IRQ_EN_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(TP_DOWN_IRQ_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `tp_up_irq_en` reader - TP Last Touch (Stylus UP) IRQ Enable"]
59pub type TP_UP_IRQ_EN_R = crate::BitReader<TP_UP_IRQ_EN_A>;
60#[doc = "TP Last Touch (Stylus UP) IRQ Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TP_UP_IRQ_EN_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<TP_UP_IRQ_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: TP_UP_IRQ_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TP_UP_IRQ_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TP_UP_IRQ_EN_A {
78        match self.bits {
79            false => TP_UP_IRQ_EN_A::DISABLE,
80            true => TP_UP_IRQ_EN_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == TP_UP_IRQ_EN_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == TP_UP_IRQ_EN_A::ENABLE
92    }
93}
94#[doc = "Field `tp_up_irq_en` writer - TP Last Touch (Stylus UP) IRQ Enable"]
95pub type TP_UP_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, TP_UP_IRQ_EN_A>;
96impl<'a, REG> TP_UP_IRQ_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(TP_UP_IRQ_EN_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(TP_UP_IRQ_EN_A::ENABLE)
109    }
110}
111#[doc = "Field `tp_fifo_flush` reader - TP FIFO Flush"]
112pub type TP_FIFO_FLUSH_R = crate::BitReader<TP_FIFO_FLUSH_A>;
113#[doc = "TP FIFO Flush\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum TP_FIFO_FLUSH_A {
116    #[doc = "1: `1`"]
117    FLUSH = 1,
118}
119impl From<TP_FIFO_FLUSH_A> for bool {
120    #[inline(always)]
121    fn from(variant: TP_FIFO_FLUSH_A) -> Self {
122        variant as u8 != 0
123    }
124}
125impl TP_FIFO_FLUSH_R {
126    #[doc = "Get enumerated values variant"]
127    #[inline(always)]
128    pub const fn variant(&self) -> Option<TP_FIFO_FLUSH_A> {
129        match self.bits {
130            true => Some(TP_FIFO_FLUSH_A::FLUSH),
131            _ => None,
132        }
133    }
134    #[doc = "`1`"]
135    #[inline(always)]
136    pub fn is_flush(&self) -> bool {
137        *self == TP_FIFO_FLUSH_A::FLUSH
138    }
139}
140#[doc = "Field `tp_fifo_flush` writer - TP FIFO Flush"]
141pub type TP_FIFO_FLUSH_W<'a, REG> = crate::BitWriter<'a, REG, TP_FIFO_FLUSH_A>;
142impl<'a, REG> TP_FIFO_FLUSH_W<'a, REG>
143where
144    REG: crate::Writable + crate::RegisterSpec,
145{
146    #[doc = "`1`"]
147    #[inline(always)]
148    pub fn flush(self) -> &'a mut crate::W<REG> {
149        self.variant(TP_FIFO_FLUSH_A::FLUSH)
150    }
151}
152#[doc = "Field `tp_data_erq_en` reader - TP FIFO Data Available DRQ Enable"]
153pub type TP_DATA_ERQ_EN_R = crate::BitReader<TP_DATA_ERQ_EN_A>;
154#[doc = "TP FIFO Data Available DRQ Enable\n\nValue on reset: 0"]
155#[derive(Clone, Copy, Debug, PartialEq, Eq)]
156pub enum TP_DATA_ERQ_EN_A {
157    #[doc = "0: `0`"]
158    DISABLE = 0,
159    #[doc = "1: `1`"]
160    ENABLE = 1,
161}
162impl From<TP_DATA_ERQ_EN_A> for bool {
163    #[inline(always)]
164    fn from(variant: TP_DATA_ERQ_EN_A) -> Self {
165        variant as u8 != 0
166    }
167}
168impl TP_DATA_ERQ_EN_R {
169    #[doc = "Get enumerated values variant"]
170    #[inline(always)]
171    pub const fn variant(&self) -> TP_DATA_ERQ_EN_A {
172        match self.bits {
173            false => TP_DATA_ERQ_EN_A::DISABLE,
174            true => TP_DATA_ERQ_EN_A::ENABLE,
175        }
176    }
177    #[doc = "`0`"]
178    #[inline(always)]
179    pub fn is_disable(&self) -> bool {
180        *self == TP_DATA_ERQ_EN_A::DISABLE
181    }
182    #[doc = "`1`"]
183    #[inline(always)]
184    pub fn is_enable(&self) -> bool {
185        *self == TP_DATA_ERQ_EN_A::ENABLE
186    }
187}
188#[doc = "Field `tp_data_erq_en` writer - TP FIFO Data Available DRQ Enable"]
189pub type TP_DATA_ERQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, TP_DATA_ERQ_EN_A>;
190impl<'a, REG> TP_DATA_ERQ_EN_W<'a, REG>
191where
192    REG: crate::Writable + crate::RegisterSpec,
193{
194    #[doc = "`0`"]
195    #[inline(always)]
196    pub fn disable(self) -> &'a mut crate::W<REG> {
197        self.variant(TP_DATA_ERQ_EN_A::DISABLE)
198    }
199    #[doc = "`1`"]
200    #[inline(always)]
201    pub fn enable(self) -> &'a mut crate::W<REG> {
202        self.variant(TP_DATA_ERQ_EN_A::ENABLE)
203    }
204}
205#[doc = "Field `tp_fifo_trig_level` reader - TP FIFO Data Available Trigger Level"]
206pub type TP_FIFO_TRIG_LEVEL_R = crate::FieldReader;
207#[doc = "Field `tp_fifo_trig_level` writer - TP FIFO Data Available Trigger Level"]
208pub type TP_FIFO_TRIG_LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
209#[doc = "Field `tp_data_xy_change` reader - TP FIFO XY Data Interchange Function Select"]
210pub type TP_DATA_XY_CHANGE_R = crate::BitReader<TP_DATA_XY_CHANGE_A>;
211#[doc = "TP FIFO XY Data Interchange Function Select\n\nValue on reset: 0"]
212#[derive(Clone, Copy, Debug, PartialEq, Eq)]
213pub enum TP_DATA_XY_CHANGE_A {
214    #[doc = "0: `0`"]
215    DISABLE = 0,
216    #[doc = "1: `1`"]
217    ENABLE = 1,
218}
219impl From<TP_DATA_XY_CHANGE_A> for bool {
220    #[inline(always)]
221    fn from(variant: TP_DATA_XY_CHANGE_A) -> Self {
222        variant as u8 != 0
223    }
224}
225impl TP_DATA_XY_CHANGE_R {
226    #[doc = "Get enumerated values variant"]
227    #[inline(always)]
228    pub const fn variant(&self) -> TP_DATA_XY_CHANGE_A {
229        match self.bits {
230            false => TP_DATA_XY_CHANGE_A::DISABLE,
231            true => TP_DATA_XY_CHANGE_A::ENABLE,
232        }
233    }
234    #[doc = "`0`"]
235    #[inline(always)]
236    pub fn is_disable(&self) -> bool {
237        *self == TP_DATA_XY_CHANGE_A::DISABLE
238    }
239    #[doc = "`1`"]
240    #[inline(always)]
241    pub fn is_enable(&self) -> bool {
242        *self == TP_DATA_XY_CHANGE_A::ENABLE
243    }
244}
245#[doc = "Field `tp_data_xy_change` writer - TP FIFO XY Data Interchange Function Select"]
246pub type TP_DATA_XY_CHANGE_W<'a, REG> = crate::BitWriter<'a, REG, TP_DATA_XY_CHANGE_A>;
247impl<'a, REG> TP_DATA_XY_CHANGE_W<'a, REG>
248where
249    REG: crate::Writable + crate::RegisterSpec,
250{
251    #[doc = "`0`"]
252    #[inline(always)]
253    pub fn disable(self) -> &'a mut crate::W<REG> {
254        self.variant(TP_DATA_XY_CHANGE_A::DISABLE)
255    }
256    #[doc = "`1`"]
257    #[inline(always)]
258    pub fn enable(self) -> &'a mut crate::W<REG> {
259        self.variant(TP_DATA_XY_CHANGE_A::ENABLE)
260    }
261}
262#[doc = "Field `tp_data_irq_en` reader - TP FIFO Data Interrupt Enable"]
263pub type TP_DATA_IRQ_EN_R = crate::BitReader<TP_DATA_IRQ_EN_A>;
264#[doc = "TP FIFO Data Interrupt Enable\n\nValue on reset: 0"]
265#[derive(Clone, Copy, Debug, PartialEq, Eq)]
266pub enum TP_DATA_IRQ_EN_A {
267    #[doc = "0: `0`"]
268    DISABLE = 0,
269    #[doc = "1: `1`"]
270    ENABLE = 1,
271}
272impl From<TP_DATA_IRQ_EN_A> for bool {
273    #[inline(always)]
274    fn from(variant: TP_DATA_IRQ_EN_A) -> Self {
275        variant as u8 != 0
276    }
277}
278impl TP_DATA_IRQ_EN_R {
279    #[doc = "Get enumerated values variant"]
280    #[inline(always)]
281    pub const fn variant(&self) -> TP_DATA_IRQ_EN_A {
282        match self.bits {
283            false => TP_DATA_IRQ_EN_A::DISABLE,
284            true => TP_DATA_IRQ_EN_A::ENABLE,
285        }
286    }
287    #[doc = "`0`"]
288    #[inline(always)]
289    pub fn is_disable(&self) -> bool {
290        *self == TP_DATA_IRQ_EN_A::DISABLE
291    }
292    #[doc = "`1`"]
293    #[inline(always)]
294    pub fn is_enable(&self) -> bool {
295        *self == TP_DATA_IRQ_EN_A::ENABLE
296    }
297}
298#[doc = "Field `tp_data_irq_en` writer - TP FIFO Data Interrupt Enable"]
299pub type TP_DATA_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, TP_DATA_IRQ_EN_A>;
300impl<'a, REG> TP_DATA_IRQ_EN_W<'a, REG>
301where
302    REG: crate::Writable + crate::RegisterSpec,
303{
304    #[doc = "`0`"]
305    #[inline(always)]
306    pub fn disable(self) -> &'a mut crate::W<REG> {
307        self.variant(TP_DATA_IRQ_EN_A::DISABLE)
308    }
309    #[doc = "`1`"]
310    #[inline(always)]
311    pub fn enable(self) -> &'a mut crate::W<REG> {
312        self.variant(TP_DATA_IRQ_EN_A::ENABLE)
313    }
314}
315#[doc = "Field `tp_overrun_irq_en` reader - TP FIFO Overrun Interrupt Enable"]
316pub type TP_OVERRUN_IRQ_EN_R = crate::BitReader<TP_OVERRUN_IRQ_EN_A>;
317#[doc = "TP FIFO Overrun Interrupt Enable\n\nValue on reset: 0"]
318#[derive(Clone, Copy, Debug, PartialEq, Eq)]
319pub enum TP_OVERRUN_IRQ_EN_A {
320    #[doc = "0: `0`"]
321    DISABLE = 0,
322    #[doc = "1: `1`"]
323    ENABLE = 1,
324}
325impl From<TP_OVERRUN_IRQ_EN_A> for bool {
326    #[inline(always)]
327    fn from(variant: TP_OVERRUN_IRQ_EN_A) -> Self {
328        variant as u8 != 0
329    }
330}
331impl TP_OVERRUN_IRQ_EN_R {
332    #[doc = "Get enumerated values variant"]
333    #[inline(always)]
334    pub const fn variant(&self) -> TP_OVERRUN_IRQ_EN_A {
335        match self.bits {
336            false => TP_OVERRUN_IRQ_EN_A::DISABLE,
337            true => TP_OVERRUN_IRQ_EN_A::ENABLE,
338        }
339    }
340    #[doc = "`0`"]
341    #[inline(always)]
342    pub fn is_disable(&self) -> bool {
343        *self == TP_OVERRUN_IRQ_EN_A::DISABLE
344    }
345    #[doc = "`1`"]
346    #[inline(always)]
347    pub fn is_enable(&self) -> bool {
348        *self == TP_OVERRUN_IRQ_EN_A::ENABLE
349    }
350}
351#[doc = "Field `tp_overrun_irq_en` writer - TP FIFO Overrun Interrupt Enable"]
352pub type TP_OVERRUN_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, TP_OVERRUN_IRQ_EN_A>;
353impl<'a, REG> TP_OVERRUN_IRQ_EN_W<'a, REG>
354where
355    REG: crate::Writable + crate::RegisterSpec,
356{
357    #[doc = "`0`"]
358    #[inline(always)]
359    pub fn disable(self) -> &'a mut crate::W<REG> {
360        self.variant(TP_OVERRUN_IRQ_EN_A::DISABLE)
361    }
362    #[doc = "`1`"]
363    #[inline(always)]
364    pub fn enable(self) -> &'a mut crate::W<REG> {
365        self.variant(TP_OVERRUN_IRQ_EN_A::ENABLE)
366    }
367}
368impl R {
369    #[doc = "Bit 0 - TP First Touch (Stylus DOWN) IRQ Enable"]
370    #[inline(always)]
371    pub fn tp_down_irq_en(&self) -> TP_DOWN_IRQ_EN_R {
372        TP_DOWN_IRQ_EN_R::new((self.bits & 1) != 0)
373    }
374    #[doc = "Bit 1 - TP Last Touch (Stylus UP) IRQ Enable"]
375    #[inline(always)]
376    pub fn tp_up_irq_en(&self) -> TP_UP_IRQ_EN_R {
377        TP_UP_IRQ_EN_R::new(((self.bits >> 1) & 1) != 0)
378    }
379    #[doc = "Bit 4 - TP FIFO Flush"]
380    #[inline(always)]
381    pub fn tp_fifo_flush(&self) -> TP_FIFO_FLUSH_R {
382        TP_FIFO_FLUSH_R::new(((self.bits >> 4) & 1) != 0)
383    }
384    #[doc = "Bit 7 - TP FIFO Data Available DRQ Enable"]
385    #[inline(always)]
386    pub fn tp_data_erq_en(&self) -> TP_DATA_ERQ_EN_R {
387        TP_DATA_ERQ_EN_R::new(((self.bits >> 7) & 1) != 0)
388    }
389    #[doc = "Bits 8:12 - TP FIFO Data Available Trigger Level"]
390    #[inline(always)]
391    pub fn tp_fifo_trig_level(&self) -> TP_FIFO_TRIG_LEVEL_R {
392        TP_FIFO_TRIG_LEVEL_R::new(((self.bits >> 8) & 0x1f) as u8)
393    }
394    #[doc = "Bit 13 - TP FIFO XY Data Interchange Function Select"]
395    #[inline(always)]
396    pub fn tp_data_xy_change(&self) -> TP_DATA_XY_CHANGE_R {
397        TP_DATA_XY_CHANGE_R::new(((self.bits >> 13) & 1) != 0)
398    }
399    #[doc = "Bit 16 - TP FIFO Data Interrupt Enable"]
400    #[inline(always)]
401    pub fn tp_data_irq_en(&self) -> TP_DATA_IRQ_EN_R {
402        TP_DATA_IRQ_EN_R::new(((self.bits >> 16) & 1) != 0)
403    }
404    #[doc = "Bit 17 - TP FIFO Overrun Interrupt Enable"]
405    #[inline(always)]
406    pub fn tp_overrun_irq_en(&self) -> TP_OVERRUN_IRQ_EN_R {
407        TP_OVERRUN_IRQ_EN_R::new(((self.bits >> 17) & 1) != 0)
408    }
409}
410impl W {
411    #[doc = "Bit 0 - TP First Touch (Stylus DOWN) IRQ Enable"]
412    #[inline(always)]
413    #[must_use]
414    pub fn tp_down_irq_en(&mut self) -> TP_DOWN_IRQ_EN_W<TP_INT_FIFO_CTRL_SPEC> {
415        TP_DOWN_IRQ_EN_W::new(self, 0)
416    }
417    #[doc = "Bit 1 - TP Last Touch (Stylus UP) IRQ Enable"]
418    #[inline(always)]
419    #[must_use]
420    pub fn tp_up_irq_en(&mut self) -> TP_UP_IRQ_EN_W<TP_INT_FIFO_CTRL_SPEC> {
421        TP_UP_IRQ_EN_W::new(self, 1)
422    }
423    #[doc = "Bit 4 - TP FIFO Flush"]
424    #[inline(always)]
425    #[must_use]
426    pub fn tp_fifo_flush(&mut self) -> TP_FIFO_FLUSH_W<TP_INT_FIFO_CTRL_SPEC> {
427        TP_FIFO_FLUSH_W::new(self, 4)
428    }
429    #[doc = "Bit 7 - TP FIFO Data Available DRQ Enable"]
430    #[inline(always)]
431    #[must_use]
432    pub fn tp_data_erq_en(&mut self) -> TP_DATA_ERQ_EN_W<TP_INT_FIFO_CTRL_SPEC> {
433        TP_DATA_ERQ_EN_W::new(self, 7)
434    }
435    #[doc = "Bits 8:12 - TP FIFO Data Available Trigger Level"]
436    #[inline(always)]
437    #[must_use]
438    pub fn tp_fifo_trig_level(&mut self) -> TP_FIFO_TRIG_LEVEL_W<TP_INT_FIFO_CTRL_SPEC> {
439        TP_FIFO_TRIG_LEVEL_W::new(self, 8)
440    }
441    #[doc = "Bit 13 - TP FIFO XY Data Interchange Function Select"]
442    #[inline(always)]
443    #[must_use]
444    pub fn tp_data_xy_change(&mut self) -> TP_DATA_XY_CHANGE_W<TP_INT_FIFO_CTRL_SPEC> {
445        TP_DATA_XY_CHANGE_W::new(self, 13)
446    }
447    #[doc = "Bit 16 - TP FIFO Data Interrupt Enable"]
448    #[inline(always)]
449    #[must_use]
450    pub fn tp_data_irq_en(&mut self) -> TP_DATA_IRQ_EN_W<TP_INT_FIFO_CTRL_SPEC> {
451        TP_DATA_IRQ_EN_W::new(self, 16)
452    }
453    #[doc = "Bit 17 - TP FIFO Overrun Interrupt Enable"]
454    #[inline(always)]
455    #[must_use]
456    pub fn tp_overrun_irq_en(&mut self) -> TP_OVERRUN_IRQ_EN_W<TP_INT_FIFO_CTRL_SPEC> {
457        TP_OVERRUN_IRQ_EN_W::new(self, 17)
458    }
459    #[doc = r" Writes raw bits to the register."]
460    #[doc = r""]
461    #[doc = r" # Safety"]
462    #[doc = r""]
463    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
464    #[inline(always)]
465    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
466        self.bits = bits;
467        self
468    }
469}
470#[doc = "TP Interrupt FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tp_int_fifo_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tp_int_fifo_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
471pub struct TP_INT_FIFO_CTRL_SPEC;
472impl crate::RegisterSpec for TP_INT_FIFO_CTRL_SPEC {
473    type Ux = u32;
474}
475#[doc = "`read()` method returns [`tp_int_fifo_ctrl::R`](R) reader structure"]
476impl crate::Readable for TP_INT_FIFO_CTRL_SPEC {}
477#[doc = "`write(|w| ..)` method takes [`tp_int_fifo_ctrl::W`](W) writer structure"]
478impl crate::Writable for TP_INT_FIFO_CTRL_SPEC {
479    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
480    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
481}
482#[doc = "`reset()` method sets tp_int_fifo_ctrl to value 0"]
483impl crate::Resettable for TP_INT_FIFO_CTRL_SPEC {
484    const RESET_VALUE: Self::Ux = 0;
485}
d1_pac/tpadc/tp_int_fifo_ctrl.rs

d1_pac/tpadc/
tp_int_fifo_ctrl.rs
