d1_pac/tpadc/
tp_ctrl0.rs

1#[doc = "Register `tp_ctrl0` reader"]
2pub type R = crate::R<TP_CTRL0_SPEC>;
3#[doc = "Register `tp_ctrl0` writer"]
4pub type W = crate::W<TP_CTRL0_SPEC>;
5#[doc = "Field `tacq` reader - Touch panel ADC acquire time"]
6pub type TACQ_R = crate::FieldReader<u16>;
7#[doc = "Field `tacq` writer - Touch panel ADC acquire time"]
8pub type TACQ_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `fs_div` reader - ADC Sample Frequency Divider"]
10pub type FS_DIV_R = crate::FieldReader<FS_DIV_A>;
11#[doc = "ADC Sample Frequency Divider\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum FS_DIV_A {
15    #[doc = "0: CLK_IN / 2 ^ (20 - 0)"]
16    C2P0 = 0,
17    #[doc = "1: CLK_IN / 2 ^ (20 - 1)"]
18    C2P1 = 1,
19    #[doc = "2: CLK_IN / 2 ^ (20 - 2)"]
20    C2P2 = 2,
21    #[doc = "3: CLK_IN / 2 ^ (20 - 3)"]
22    C2P3 = 3,
23    #[doc = "4: CLK_IN / 2 ^ (20 - 4)"]
24    C2P4 = 4,
25    #[doc = "5: CLK_IN / 2 ^ (20 - 5)"]
26    C2P5 = 5,
27    #[doc = "6: CLK_IN / 2 ^ (20 - 6)"]
28    C2P6 = 6,
29    #[doc = "7: CLK_IN / 2 ^ (20 - 7)"]
30    C2P7 = 7,
31    #[doc = "8: CLK_IN / 2 ^ (20 - 8)"]
32    C2P8 = 8,
33    #[doc = "9: CLK_IN / 2 ^ (20 - 9)"]
34    C2P9 = 9,
35    #[doc = "10: CLK_IN / 2 ^ (20 - 10)"]
36    C2P10 = 10,
37    #[doc = "11: CLK_IN / 2 ^ (20 - 11)"]
38    C2P11 = 11,
39    #[doc = "12: CLK_IN / 2 ^ (20 - 12)"]
40    C2P12 = 12,
41    #[doc = "13: CLK_IN / 2 ^ (20 - 13)"]
42    C2P13 = 13,
43    #[doc = "14: CLK_IN / 2 ^ (20 - 14)"]
44    C2P14 = 14,
45    #[doc = "15: CLK_IN / 2 ^ (20 - 15)"]
46    C2P15 = 15,
47}
48impl From<FS_DIV_A> for u8 {
49    #[inline(always)]
50    fn from(variant: FS_DIV_A) -> Self {
51        variant as _
52    }
53}
54impl crate::FieldSpec for FS_DIV_A {
55    type Ux = u8;
56}
57impl FS_DIV_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub const fn variant(&self) -> FS_DIV_A {
61        match self.bits {
62            0 => FS_DIV_A::C2P0,
63            1 => FS_DIV_A::C2P1,
64            2 => FS_DIV_A::C2P2,
65            3 => FS_DIV_A::C2P3,
66            4 => FS_DIV_A::C2P4,
67            5 => FS_DIV_A::C2P5,
68            6 => FS_DIV_A::C2P6,
69            7 => FS_DIV_A::C2P7,
70            8 => FS_DIV_A::C2P8,
71            9 => FS_DIV_A::C2P9,
72            10 => FS_DIV_A::C2P10,
73            11 => FS_DIV_A::C2P11,
74            12 => FS_DIV_A::C2P12,
75            13 => FS_DIV_A::C2P13,
76            14 => FS_DIV_A::C2P14,
77            15 => FS_DIV_A::C2P15,
78            _ => unreachable!(),
79        }
80    }
81    #[doc = "CLK_IN / 2 ^ (20 - 0)"]
82    #[inline(always)]
83    pub fn is_c2p0(&self) -> bool {
84        *self == FS_DIV_A::C2P0
85    }
86    #[doc = "CLK_IN / 2 ^ (20 - 1)"]
87    #[inline(always)]
88    pub fn is_c2p1(&self) -> bool {
89        *self == FS_DIV_A::C2P1
90    }
91    #[doc = "CLK_IN / 2 ^ (20 - 2)"]
92    #[inline(always)]
93    pub fn is_c2p2(&self) -> bool {
94        *self == FS_DIV_A::C2P2
95    }
96    #[doc = "CLK_IN / 2 ^ (20 - 3)"]
97    #[inline(always)]
98    pub fn is_c2p3(&self) -> bool {
99        *self == FS_DIV_A::C2P3
100    }
101    #[doc = "CLK_IN / 2 ^ (20 - 4)"]
102    #[inline(always)]
103    pub fn is_c2p4(&self) -> bool {
104        *self == FS_DIV_A::C2P4
105    }
106    #[doc = "CLK_IN / 2 ^ (20 - 5)"]
107    #[inline(always)]
108    pub fn is_c2p5(&self) -> bool {
109        *self == FS_DIV_A::C2P5
110    }
111    #[doc = "CLK_IN / 2 ^ (20 - 6)"]
112    #[inline(always)]
113    pub fn is_c2p6(&self) -> bool {
114        *self == FS_DIV_A::C2P6
115    }
116    #[doc = "CLK_IN / 2 ^ (20 - 7)"]
117    #[inline(always)]
118    pub fn is_c2p7(&self) -> bool {
119        *self == FS_DIV_A::C2P7
120    }
121    #[doc = "CLK_IN / 2 ^ (20 - 8)"]
122    #[inline(always)]
123    pub fn is_c2p8(&self) -> bool {
124        *self == FS_DIV_A::C2P8
125    }
126    #[doc = "CLK_IN / 2 ^ (20 - 9)"]
127    #[inline(always)]
128    pub fn is_c2p9(&self) -> bool {
129        *self == FS_DIV_A::C2P9
130    }
131    #[doc = "CLK_IN / 2 ^ (20 - 10)"]
132    #[inline(always)]
133    pub fn is_c2p10(&self) -> bool {
134        *self == FS_DIV_A::C2P10
135    }
136    #[doc = "CLK_IN / 2 ^ (20 - 11)"]
137    #[inline(always)]
138    pub fn is_c2p11(&self) -> bool {
139        *self == FS_DIV_A::C2P11
140    }
141    #[doc = "CLK_IN / 2 ^ (20 - 12)"]
142    #[inline(always)]
143    pub fn is_c2p12(&self) -> bool {
144        *self == FS_DIV_A::C2P12
145    }
146    #[doc = "CLK_IN / 2 ^ (20 - 13)"]
147    #[inline(always)]
148    pub fn is_c2p13(&self) -> bool {
149        *self == FS_DIV_A::C2P13
150    }
151    #[doc = "CLK_IN / 2 ^ (20 - 14)"]
152    #[inline(always)]
153    pub fn is_c2p14(&self) -> bool {
154        *self == FS_DIV_A::C2P14
155    }
156    #[doc = "CLK_IN / 2 ^ (20 - 15)"]
157    #[inline(always)]
158    pub fn is_c2p15(&self) -> bool {
159        *self == FS_DIV_A::C2P15
160    }
161}
162#[doc = "Field `fs_div` writer - ADC Sample Frequency Divider"]
163pub type FS_DIV_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 4, FS_DIV_A>;
164impl<'a, REG> FS_DIV_W<'a, REG>
165where
166    REG: crate::Writable + crate::RegisterSpec,
167    REG::Ux: From<u8>,
168{
169    #[doc = "CLK_IN / 2 ^ (20 - 0)"]
170    #[inline(always)]
171    pub fn c2p0(self) -> &'a mut crate::W<REG> {
172        self.variant(FS_DIV_A::C2P0)
173    }
174    #[doc = "CLK_IN / 2 ^ (20 - 1)"]
175    #[inline(always)]
176    pub fn c2p1(self) -> &'a mut crate::W<REG> {
177        self.variant(FS_DIV_A::C2P1)
178    }
179    #[doc = "CLK_IN / 2 ^ (20 - 2)"]
180    #[inline(always)]
181    pub fn c2p2(self) -> &'a mut crate::W<REG> {
182        self.variant(FS_DIV_A::C2P2)
183    }
184    #[doc = "CLK_IN / 2 ^ (20 - 3)"]
185    #[inline(always)]
186    pub fn c2p3(self) -> &'a mut crate::W<REG> {
187        self.variant(FS_DIV_A::C2P3)
188    }
189    #[doc = "CLK_IN / 2 ^ (20 - 4)"]
190    #[inline(always)]
191    pub fn c2p4(self) -> &'a mut crate::W<REG> {
192        self.variant(FS_DIV_A::C2P4)
193    }
194    #[doc = "CLK_IN / 2 ^ (20 - 5)"]
195    #[inline(always)]
196    pub fn c2p5(self) -> &'a mut crate::W<REG> {
197        self.variant(FS_DIV_A::C2P5)
198    }
199    #[doc = "CLK_IN / 2 ^ (20 - 6)"]
200    #[inline(always)]
201    pub fn c2p6(self) -> &'a mut crate::W<REG> {
202        self.variant(FS_DIV_A::C2P6)
203    }
204    #[doc = "CLK_IN / 2 ^ (20 - 7)"]
205    #[inline(always)]
206    pub fn c2p7(self) -> &'a mut crate::W<REG> {
207        self.variant(FS_DIV_A::C2P7)
208    }
209    #[doc = "CLK_IN / 2 ^ (20 - 8)"]
210    #[inline(always)]
211    pub fn c2p8(self) -> &'a mut crate::W<REG> {
212        self.variant(FS_DIV_A::C2P8)
213    }
214    #[doc = "CLK_IN / 2 ^ (20 - 9)"]
215    #[inline(always)]
216    pub fn c2p9(self) -> &'a mut crate::W<REG> {
217        self.variant(FS_DIV_A::C2P9)
218    }
219    #[doc = "CLK_IN / 2 ^ (20 - 10)"]
220    #[inline(always)]
221    pub fn c2p10(self) -> &'a mut crate::W<REG> {
222        self.variant(FS_DIV_A::C2P10)
223    }
224    #[doc = "CLK_IN / 2 ^ (20 - 11)"]
225    #[inline(always)]
226    pub fn c2p11(self) -> &'a mut crate::W<REG> {
227        self.variant(FS_DIV_A::C2P11)
228    }
229    #[doc = "CLK_IN / 2 ^ (20 - 12)"]
230    #[inline(always)]
231    pub fn c2p12(self) -> &'a mut crate::W<REG> {
232        self.variant(FS_DIV_A::C2P12)
233    }
234    #[doc = "CLK_IN / 2 ^ (20 - 13)"]
235    #[inline(always)]
236    pub fn c2p13(self) -> &'a mut crate::W<REG> {
237        self.variant(FS_DIV_A::C2P13)
238    }
239    #[doc = "CLK_IN / 2 ^ (20 - 14)"]
240    #[inline(always)]
241    pub fn c2p14(self) -> &'a mut crate::W<REG> {
242        self.variant(FS_DIV_A::C2P14)
243    }
244    #[doc = "CLK_IN / 2 ^ (20 - 15)"]
245    #[inline(always)]
246    pub fn c2p15(self) -> &'a mut crate::W<REG> {
247        self.variant(FS_DIV_A::C2P15)
248    }
249}
250#[doc = "Field `adc_clk_divider` reader - ADC Clock Divider (CLK_IN)"]
251pub type ADC_CLK_DIVIDER_R = crate::FieldReader<ADC_CLK_DIVIDER_A>;
252#[doc = "ADC Clock Divider (CLK_IN)\n\nValue on reset: 0"]
253#[derive(Clone, Copy, Debug, PartialEq, Eq)]
254#[repr(u8)]
255pub enum ADC_CLK_DIVIDER_A {
256    #[doc = "0: CLK / 2"]
257    C2 = 0,
258    #[doc = "1: CLK / 3"]
259    C3 = 1,
260    #[doc = "2: CLK / 6"]
261    C6 = 2,
262    #[doc = "3: CLK / 1"]
263    C1 = 3,
264}
265impl From<ADC_CLK_DIVIDER_A> for u8 {
266    #[inline(always)]
267    fn from(variant: ADC_CLK_DIVIDER_A) -> Self {
268        variant as _
269    }
270}
271impl crate::FieldSpec for ADC_CLK_DIVIDER_A {
272    type Ux = u8;
273}
274impl ADC_CLK_DIVIDER_R {
275    #[doc = "Get enumerated values variant"]
276    #[inline(always)]
277    pub const fn variant(&self) -> ADC_CLK_DIVIDER_A {
278        match self.bits {
279            0 => ADC_CLK_DIVIDER_A::C2,
280            1 => ADC_CLK_DIVIDER_A::C3,
281            2 => ADC_CLK_DIVIDER_A::C6,
282            3 => ADC_CLK_DIVIDER_A::C1,
283            _ => unreachable!(),
284        }
285    }
286    #[doc = "CLK / 2"]
287    #[inline(always)]
288    pub fn is_c2(&self) -> bool {
289        *self == ADC_CLK_DIVIDER_A::C2
290    }
291    #[doc = "CLK / 3"]
292    #[inline(always)]
293    pub fn is_c3(&self) -> bool {
294        *self == ADC_CLK_DIVIDER_A::C3
295    }
296    #[doc = "CLK / 6"]
297    #[inline(always)]
298    pub fn is_c6(&self) -> bool {
299        *self == ADC_CLK_DIVIDER_A::C6
300    }
301    #[doc = "CLK / 1"]
302    #[inline(always)]
303    pub fn is_c1(&self) -> bool {
304        *self == ADC_CLK_DIVIDER_A::C1
305    }
306}
307#[doc = "Field `adc_clk_divider` writer - ADC Clock Divider (CLK_IN)"]
308pub type ADC_CLK_DIVIDER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ADC_CLK_DIVIDER_A>;
309impl<'a, REG> ADC_CLK_DIVIDER_W<'a, REG>
310where
311    REG: crate::Writable + crate::RegisterSpec,
312    REG::Ux: From<u8>,
313{
314    #[doc = "CLK / 2"]
315    #[inline(always)]
316    pub fn c2(self) -> &'a mut crate::W<REG> {
317        self.variant(ADC_CLK_DIVIDER_A::C2)
318    }
319    #[doc = "CLK / 3"]
320    #[inline(always)]
321    pub fn c3(self) -> &'a mut crate::W<REG> {
322        self.variant(ADC_CLK_DIVIDER_A::C3)
323    }
324    #[doc = "CLK / 6"]
325    #[inline(always)]
326    pub fn c6(self) -> &'a mut crate::W<REG> {
327        self.variant(ADC_CLK_DIVIDER_A::C6)
328    }
329    #[doc = "CLK / 1"]
330    #[inline(always)]
331    pub fn c1(self) -> &'a mut crate::W<REG> {
332        self.variant(ADC_CLK_DIVIDER_A::C1)
333    }
334}
335#[doc = "Field `adc_first_dly_mode` reader - ADC First Convert Delay Mode Select"]
336pub type ADC_FIRST_DLY_MODE_R = crate::BitReader<ADC_FIRST_DLY_MODE_A>;
337#[doc = "ADC First Convert Delay Mode Select\n\nValue on reset: 0"]
338#[derive(Clone, Copy, Debug, PartialEq, Eq)]
339pub enum ADC_FIRST_DLY_MODE_A {
340    #[doc = "0: CLK_IN / 16"]
341    C16 = 0,
342    #[doc = "1: CLK_IN / 16 * 256"]
343    C16_256 = 1,
344}
345impl From<ADC_FIRST_DLY_MODE_A> for bool {
346    #[inline(always)]
347    fn from(variant: ADC_FIRST_DLY_MODE_A) -> Self {
348        variant as u8 != 0
349    }
350}
351impl ADC_FIRST_DLY_MODE_R {
352    #[doc = "Get enumerated values variant"]
353    #[inline(always)]
354    pub const fn variant(&self) -> ADC_FIRST_DLY_MODE_A {
355        match self.bits {
356            false => ADC_FIRST_DLY_MODE_A::C16,
357            true => ADC_FIRST_DLY_MODE_A::C16_256,
358        }
359    }
360    #[doc = "CLK_IN / 16"]
361    #[inline(always)]
362    pub fn is_c16(&self) -> bool {
363        *self == ADC_FIRST_DLY_MODE_A::C16
364    }
365    #[doc = "CLK_IN / 16 * 256"]
366    #[inline(always)]
367    pub fn is_c16_256(&self) -> bool {
368        *self == ADC_FIRST_DLY_MODE_A::C16_256
369    }
370}
371#[doc = "Field `adc_first_dly_mode` writer - ADC First Convert Delay Mode Select"]
372pub type ADC_FIRST_DLY_MODE_W<'a, REG> = crate::BitWriter<'a, REG, ADC_FIRST_DLY_MODE_A>;
373impl<'a, REG> ADC_FIRST_DLY_MODE_W<'a, REG>
374where
375    REG: crate::Writable + crate::RegisterSpec,
376{
377    #[doc = "CLK_IN / 16"]
378    #[inline(always)]
379    pub fn c16(self) -> &'a mut crate::W<REG> {
380        self.variant(ADC_FIRST_DLY_MODE_A::C16)
381    }
382    #[doc = "CLK_IN / 16 * 256"]
383    #[inline(always)]
384    pub fn c16_256(self) -> &'a mut crate::W<REG> {
385        self.variant(ADC_FIRST_DLY_MODE_A::C16_256)
386    }
387}
388#[doc = "Field `adc_first_dly` reader - ADC First Convert Delay Time (T_FCDT) Setting"]
389pub type ADC_FIRST_DLY_R = crate::FieldReader;
390#[doc = "Field `adc_first_dly` writer - ADC First Convert Delay Time (T_FCDT) Setting"]
391pub type ADC_FIRST_DLY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
392impl R {
393    #[doc = "Bits 0:15 - Touch panel ADC acquire time"]
394    #[inline(always)]
395    pub fn tacq(&self) -> TACQ_R {
396        TACQ_R::new((self.bits & 0xffff) as u16)
397    }
398    #[doc = "Bits 16:19 - ADC Sample Frequency Divider"]
399    #[inline(always)]
400    pub fn fs_div(&self) -> FS_DIV_R {
401        FS_DIV_R::new(((self.bits >> 16) & 0x0f) as u8)
402    }
403    #[doc = "Bits 20:21 - ADC Clock Divider (CLK_IN)"]
404    #[inline(always)]
405    pub fn adc_clk_divider(&self) -> ADC_CLK_DIVIDER_R {
406        ADC_CLK_DIVIDER_R::new(((self.bits >> 20) & 3) as u8)
407    }
408    #[doc = "Bit 23 - ADC First Convert Delay Mode Select"]
409    #[inline(always)]
410    pub fn adc_first_dly_mode(&self) -> ADC_FIRST_DLY_MODE_R {
411        ADC_FIRST_DLY_MODE_R::new(((self.bits >> 23) & 1) != 0)
412    }
413    #[doc = "Bits 24:31 - ADC First Convert Delay Time (T_FCDT) Setting"]
414    #[inline(always)]
415    pub fn adc_first_dly(&self) -> ADC_FIRST_DLY_R {
416        ADC_FIRST_DLY_R::new(((self.bits >> 24) & 0xff) as u8)
417    }
418}
419impl W {
420    #[doc = "Bits 0:15 - Touch panel ADC acquire time"]
421    #[inline(always)]
422    #[must_use]
423    pub fn tacq(&mut self) -> TACQ_W<TP_CTRL0_SPEC> {
424        TACQ_W::new(self, 0)
425    }
426    #[doc = "Bits 16:19 - ADC Sample Frequency Divider"]
427    #[inline(always)]
428    #[must_use]
429    pub fn fs_div(&mut self) -> FS_DIV_W<TP_CTRL0_SPEC> {
430        FS_DIV_W::new(self, 16)
431    }
432    #[doc = "Bits 20:21 - ADC Clock Divider (CLK_IN)"]
433    #[inline(always)]
434    #[must_use]
435    pub fn adc_clk_divider(&mut self) -> ADC_CLK_DIVIDER_W<TP_CTRL0_SPEC> {
436        ADC_CLK_DIVIDER_W::new(self, 20)
437    }
438    #[doc = "Bit 23 - ADC First Convert Delay Mode Select"]
439    #[inline(always)]
440    #[must_use]
441    pub fn adc_first_dly_mode(&mut self) -> ADC_FIRST_DLY_MODE_W<TP_CTRL0_SPEC> {
442        ADC_FIRST_DLY_MODE_W::new(self, 23)
443    }
444    #[doc = "Bits 24:31 - ADC First Convert Delay Time (T_FCDT) Setting"]
445    #[inline(always)]
446    #[must_use]
447    pub fn adc_first_dly(&mut self) -> ADC_FIRST_DLY_W<TP_CTRL0_SPEC> {
448        ADC_FIRST_DLY_W::new(self, 24)
449    }
450    #[doc = r" Writes raw bits to the register."]
451    #[doc = r""]
452    #[doc = r" # Safety"]
453    #[doc = r""]
454    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
455    #[inline(always)]
456    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
457        self.bits = bits;
458        self
459    }
460}
461#[doc = "TP Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tp_ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tp_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
462pub struct TP_CTRL0_SPEC;
463impl crate::RegisterSpec for TP_CTRL0_SPEC {
464    type Ux = u32;
465}
466#[doc = "`read()` method returns [`tp_ctrl0::R`](R) reader structure"]
467impl crate::Readable for TP_CTRL0_SPEC {}
468#[doc = "`write(|w| ..)` method takes [`tp_ctrl0::W`](W) writer structure"]
469impl crate::Writable for TP_CTRL0_SPEC {
470    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
471    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
472}
473#[doc = "`reset()` method sets tp_ctrl0 to value 0"]
474impl crate::Resettable for TP_CTRL0_SPEC {
475    const RESET_VALUE: Self::Ux = 0;
476}
d1_pac/tpadc/tp_ctrl0.rs

d1_pac/tpadc/
tp_ctrl0.rs
