d1_pac/timer/
tmr_irq_sta.rs

1#[doc = "Register `tmr_irq_sta` reader"]
2pub type R = crate::R<TMR_IRQ_STA_SPEC>;
3#[doc = "Register `tmr_irq_sta` writer"]
4pub type W = crate::W<TMR_IRQ_STA_SPEC>;
5#[doc = "Field `tmr0_irq_pend` reader - "]
6pub type TMR0_IRQ_PEND_R = crate::BitReader<TMR0_IRQ_PEND_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TMR0_IRQ_PEND_A {
10    #[doc = "0: `0`"]
11    NO_EFFECT = 0,
12    #[doc = "1: Indicates that the interval value of the timer 0 is reached. Write 1 to clear the pending status."]
13    PENDING = 1,
14}
15impl From<TMR0_IRQ_PEND_A> for bool {
16    #[inline(always)]
17    fn from(variant: TMR0_IRQ_PEND_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TMR0_IRQ_PEND_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TMR0_IRQ_PEND_A {
25        match self.bits {
26            false => TMR0_IRQ_PEND_A::NO_EFFECT,
27            true => TMR0_IRQ_PEND_A::PENDING,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_no_effect(&self) -> bool {
33        *self == TMR0_IRQ_PEND_A::NO_EFFECT
34    }
35    #[doc = "Indicates that the interval value of the timer 0 is reached. Write 1 to clear the pending status."]
36    #[inline(always)]
37    pub fn is_pending(&self) -> bool {
38        *self == TMR0_IRQ_PEND_A::PENDING
39    }
40}
41#[doc = "Field `tmr0_irq_pend` writer - "]
42pub type TMR0_IRQ_PEND_W<'a, REG> = crate::BitWriter<'a, REG, TMR0_IRQ_PEND_A>;
43impl<'a, REG> TMR0_IRQ_PEND_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn no_effect(self) -> &'a mut crate::W<REG> {
50        self.variant(TMR0_IRQ_PEND_A::NO_EFFECT)
51    }
52    #[doc = "Indicates that the interval value of the timer 0 is reached. Write 1 to clear the pending status."]
53    #[inline(always)]
54    pub fn pending(self) -> &'a mut crate::W<REG> {
55        self.variant(TMR0_IRQ_PEND_A::PENDING)
56    }
57}
58#[doc = "Field `tmr1_irq_pend` reader - "]
59pub type TMR1_IRQ_PEND_R = crate::BitReader<TMR1_IRQ_PEND_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TMR1_IRQ_PEND_A {
63    #[doc = "0: `0`"]
64    NO_EFFECT = 0,
65    #[doc = "1: Indicates that the interval value of the timer 1 is reached. Write 1 to clear the pending status."]
66    PENDING = 1,
67}
68impl From<TMR1_IRQ_PEND_A> for bool {
69    #[inline(always)]
70    fn from(variant: TMR1_IRQ_PEND_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TMR1_IRQ_PEND_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TMR1_IRQ_PEND_A {
78        match self.bits {
79            false => TMR1_IRQ_PEND_A::NO_EFFECT,
80            true => TMR1_IRQ_PEND_A::PENDING,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_no_effect(&self) -> bool {
86        *self == TMR1_IRQ_PEND_A::NO_EFFECT
87    }
88    #[doc = "Indicates that the interval value of the timer 1 is reached. Write 1 to clear the pending status."]
89    #[inline(always)]
90    pub fn is_pending(&self) -> bool {
91        *self == TMR1_IRQ_PEND_A::PENDING
92    }
93}
94#[doc = "Field `tmr1_irq_pend` writer - "]
95pub type TMR1_IRQ_PEND_W<'a, REG> = crate::BitWriter<'a, REG, TMR1_IRQ_PEND_A>;
96impl<'a, REG> TMR1_IRQ_PEND_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn no_effect(self) -> &'a mut crate::W<REG> {
103        self.variant(TMR1_IRQ_PEND_A::NO_EFFECT)
104    }
105    #[doc = "Indicates that the interval value of the timer 1 is reached. Write 1 to clear the pending status."]
106    #[inline(always)]
107    pub fn pending(self) -> &'a mut crate::W<REG> {
108        self.variant(TMR1_IRQ_PEND_A::PENDING)
109    }
110}
111impl R {
112    #[doc = "Bit 0"]
113    #[inline(always)]
114    pub fn tmr0_irq_pend(&self) -> TMR0_IRQ_PEND_R {
115        TMR0_IRQ_PEND_R::new((self.bits & 1) != 0)
116    }
117    #[doc = "Bit 1"]
118    #[inline(always)]
119    pub fn tmr1_irq_pend(&self) -> TMR1_IRQ_PEND_R {
120        TMR1_IRQ_PEND_R::new(((self.bits >> 1) & 1) != 0)
121    }
122}
123impl W {
124    #[doc = "Bit 0"]
125    #[inline(always)]
126    #[must_use]
127    pub fn tmr0_irq_pend(&mut self) -> TMR0_IRQ_PEND_W<TMR_IRQ_STA_SPEC> {
128        TMR0_IRQ_PEND_W::new(self, 0)
129    }
130    #[doc = "Bit 1"]
131    #[inline(always)]
132    #[must_use]
133    pub fn tmr1_irq_pend(&mut self) -> TMR1_IRQ_PEND_W<TMR_IRQ_STA_SPEC> {
134        TMR1_IRQ_PEND_W::new(self, 1)
135    }
136    #[doc = r" Writes raw bits to the register."]
137    #[doc = r""]
138    #[doc = r" # Safety"]
139    #[doc = r""]
140    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
141    #[inline(always)]
142    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
143        self.bits = bits;
144        self
145    }
146}
147#[doc = "Timer Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmr_irq_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmr_irq_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
148pub struct TMR_IRQ_STA_SPEC;
149impl crate::RegisterSpec for TMR_IRQ_STA_SPEC {
150    type Ux = u32;
151}
152#[doc = "`read()` method returns [`tmr_irq_sta::R`](R) reader structure"]
153impl crate::Readable for TMR_IRQ_STA_SPEC {}
154#[doc = "`write(|w| ..)` method takes [`tmr_irq_sta::W`](W) writer structure"]
155impl crate::Writable for TMR_IRQ_STA_SPEC {
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
158}
159#[doc = "`reset()` method sets tmr_irq_sta to value 0"]
160impl crate::Resettable for TMR_IRQ_STA_SPEC {
161    const RESET_VALUE: Self::Ux = 0;
162}
d1_pac/timer/tmr_irq_sta.rs

d1_pac/timer/
tmr_irq_sta.rs
