d1_pac/timer/
avs_cnt_div.rs

1#[doc = "Register `avs_cnt_div` reader"]
2pub type R = crate::R<AVS_CNT_DIV_SPEC>;
3#[doc = "Register `avs_cnt_div` writer"]
4pub type W = crate::W<AVS_CNT_DIV_SPEC>;
5#[doc = "Field `avs_cnt_d[0-1]` reader - The divisor factor of AVS"]
6pub type AVS_CNT_D_R = crate::FieldReader<u16>;
7#[doc = "Field `avs_cnt_d[0-1]` writer - The divisor factor of AVS"]
8pub type AVS_CNT_D_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9impl R {
10    #[doc = "The divisor factor of AVS\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `avs_cnt0_d` field"]
11    #[inline(always)]
12    pub fn avs_cnt_d(&self, n: u8) -> AVS_CNT_D_R {
13        #[allow(clippy::no_effect)]
14        [(); 2][n as usize];
15        AVS_CNT_D_R::new(((self.bits >> (n * 16)) & 0x0fff) as u16)
16    }
17    #[doc = "Bits 0:11 - The divisor factor of AVS"]
18    #[inline(always)]
19    pub fn avs_cnt0_d(&self) -> AVS_CNT_D_R {
20        AVS_CNT_D_R::new((self.bits & 0x0fff) as u16)
21    }
22    #[doc = "Bits 16:27 - The divisor factor of AVS"]
23    #[inline(always)]
24    pub fn avs_cnt1_d(&self) -> AVS_CNT_D_R {
25        AVS_CNT_D_R::new(((self.bits >> 16) & 0x0fff) as u16)
26    }
27}
28impl W {
29    #[doc = "The divisor factor of AVS\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `avs_cnt0_d` field"]
30    #[inline(always)]
31    #[must_use]
32    pub fn avs_cnt_d(&mut self, n: u8) -> AVS_CNT_D_W<AVS_CNT_DIV_SPEC> {
33        #[allow(clippy::no_effect)]
34        [(); 2][n as usize];
35        AVS_CNT_D_W::new(self, n * 16)
36    }
37    #[doc = "Bits 0:11 - The divisor factor of AVS"]
38    #[inline(always)]
39    #[must_use]
40    pub fn avs_cnt0_d(&mut self) -> AVS_CNT_D_W<AVS_CNT_DIV_SPEC> {
41        AVS_CNT_D_W::new(self, 0)
42    }
43    #[doc = "Bits 16:27 - The divisor factor of AVS"]
44    #[inline(always)]
45    #[must_use]
46    pub fn avs_cnt1_d(&mut self) -> AVS_CNT_D_W<AVS_CNT_DIV_SPEC> {
47        AVS_CNT_D_W::new(self, 16)
48    }
49    #[doc = r" Writes raw bits to the register."]
50    #[doc = r""]
51    #[doc = r" # Safety"]
52    #[doc = r""]
53    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
54    #[inline(always)]
55    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
56        self.bits = bits;
57        self
58    }
59}
60#[doc = "AVS Counter Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`avs_cnt_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`avs_cnt_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct AVS_CNT_DIV_SPEC;
62impl crate::RegisterSpec for AVS_CNT_DIV_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`avs_cnt_div::R`](R) reader structure"]
66impl crate::Readable for AVS_CNT_DIV_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`avs_cnt_div::W`](W) writer structure"]
68impl crate::Writable for AVS_CNT_DIV_SPEC {
69    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
70    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
71}
72#[doc = "`reset()` method sets avs_cnt_div to value 0"]
73impl crate::Resettable for AVS_CNT_DIV_SPEC {
74    const RESET_VALUE: Self::Ux = 0;
75}
d1_pac/timer/avs_cnt_div.rs

d1_pac/timer/
avs_cnt_div.rs
