d1_pac/tcon_tv0/
tv_io_tri.rs

1#[doc = "Register `tv_io_tri` reader"]
2pub type R = crate::R<TV_IO_TRI_SPEC>;
3#[doc = "Register `tv_io_tri` writer"]
4pub type W = crate::W<TV_IO_TRI_SPEC>;
5#[doc = "Field `io_output_tri_en[0-3]` reader - IO\\[i\\] Output Trigger Enable"]
6pub type IO_OUTPUT_TRI_EN_R = crate::BitReader<IO_OUTPUT_TRI_EN_A>;
7#[doc = "IO\\[i\\] Output Trigger Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum IO_OUTPUT_TRI_EN_A {
10    #[doc = "1: Disable"]
11    DISABLE = 1,
12    #[doc = "0: Enable"]
13    ENABLE = 0,
14}
15impl From<IO_OUTPUT_TRI_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: IO_OUTPUT_TRI_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl IO_OUTPUT_TRI_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> IO_OUTPUT_TRI_EN_A {
25        match self.bits {
26            true => IO_OUTPUT_TRI_EN_A::DISABLE,
27            false => IO_OUTPUT_TRI_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == IO_OUTPUT_TRI_EN_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == IO_OUTPUT_TRI_EN_A::ENABLE
39    }
40}
41#[doc = "Field `io_output_tri_en[0-3]` writer - IO\\[i\\] Output Trigger Enable"]
42pub type IO_OUTPUT_TRI_EN_W<'a, REG> = crate::BitWriter<'a, REG, IO_OUTPUT_TRI_EN_A>;
43impl<'a, REG> IO_OUTPUT_TRI_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(IO_OUTPUT_TRI_EN_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(IO_OUTPUT_TRI_EN_A::ENABLE)
56    }
57}
58impl R {
59    #[doc = "IO\\[i\\] Output Trigger Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `io0_output_tri_en` field"]
60    #[inline(always)]
61    pub fn io_output_tri_en(&self, n: u8) -> IO_OUTPUT_TRI_EN_R {
62        #[allow(clippy::no_effect)]
63        [(); 4][n as usize];
64        IO_OUTPUT_TRI_EN_R::new(((self.bits >> (n + 24)) & 1) != 0)
65    }
66    #[doc = "Bit 24 - IO\\[i\\] Output Trigger Enable"]
67    #[inline(always)]
68    pub fn io0_output_tri_en(&self) -> IO_OUTPUT_TRI_EN_R {
69        IO_OUTPUT_TRI_EN_R::new(((self.bits >> 24) & 1) != 0)
70    }
71    #[doc = "Bit 25 - IO\\[i\\] Output Trigger Enable"]
72    #[inline(always)]
73    pub fn io1_output_tri_en(&self) -> IO_OUTPUT_TRI_EN_R {
74        IO_OUTPUT_TRI_EN_R::new(((self.bits >> 25) & 1) != 0)
75    }
76    #[doc = "Bit 26 - IO\\[i\\] Output Trigger Enable"]
77    #[inline(always)]
78    pub fn io2_output_tri_en(&self) -> IO_OUTPUT_TRI_EN_R {
79        IO_OUTPUT_TRI_EN_R::new(((self.bits >> 26) & 1) != 0)
80    }
81    #[doc = "Bit 27 - IO\\[i\\] Output Trigger Enable"]
82    #[inline(always)]
83    pub fn io3_output_tri_en(&self) -> IO_OUTPUT_TRI_EN_R {
84        IO_OUTPUT_TRI_EN_R::new(((self.bits >> 27) & 1) != 0)
85    }
86}
87impl W {
88    #[doc = "IO\\[i\\] Output Trigger Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `io0_output_tri_en` field"]
89    #[inline(always)]
90    #[must_use]
91    pub fn io_output_tri_en(&mut self, n: u8) -> IO_OUTPUT_TRI_EN_W<TV_IO_TRI_SPEC> {
92        #[allow(clippy::no_effect)]
93        [(); 4][n as usize];
94        IO_OUTPUT_TRI_EN_W::new(self, n + 24)
95    }
96    #[doc = "Bit 24 - IO\\[i\\] Output Trigger Enable"]
97    #[inline(always)]
98    #[must_use]
99    pub fn io0_output_tri_en(&mut self) -> IO_OUTPUT_TRI_EN_W<TV_IO_TRI_SPEC> {
100        IO_OUTPUT_TRI_EN_W::new(self, 24)
101    }
102    #[doc = "Bit 25 - IO\\[i\\] Output Trigger Enable"]
103    #[inline(always)]
104    #[must_use]
105    pub fn io1_output_tri_en(&mut self) -> IO_OUTPUT_TRI_EN_W<TV_IO_TRI_SPEC> {
106        IO_OUTPUT_TRI_EN_W::new(self, 25)
107    }
108    #[doc = "Bit 26 - IO\\[i\\] Output Trigger Enable"]
109    #[inline(always)]
110    #[must_use]
111    pub fn io2_output_tri_en(&mut self) -> IO_OUTPUT_TRI_EN_W<TV_IO_TRI_SPEC> {
112        IO_OUTPUT_TRI_EN_W::new(self, 26)
113    }
114    #[doc = "Bit 27 - IO\\[i\\] Output Trigger Enable"]
115    #[inline(always)]
116    #[must_use]
117    pub fn io3_output_tri_en(&mut self) -> IO_OUTPUT_TRI_EN_W<TV_IO_TRI_SPEC> {
118        IO_OUTPUT_TRI_EN_W::new(self, 27)
119    }
120    #[doc = r" Writes raw bits to the register."]
121    #[doc = r""]
122    #[doc = r" # Safety"]
123    #[doc = r""]
124    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
125    #[inline(always)]
126    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127        self.bits = bits;
128        self
129    }
130}
131#[doc = "TV SYNC Signal IO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tv_io_tri::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tv_io_tri::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
132pub struct TV_IO_TRI_SPEC;
133impl crate::RegisterSpec for TV_IO_TRI_SPEC {
134    type Ux = u32;
135}
136#[doc = "`read()` method returns [`tv_io_tri::R`](R) reader structure"]
137impl crate::Readable for TV_IO_TRI_SPEC {}
138#[doc = "`write(|w| ..)` method takes [`tv_io_tri::W`](W) writer structure"]
139impl crate::Writable for TV_IO_TRI_SPEC {
140    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
141    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
142}
143#[doc = "`reset()` method sets tv_io_tri to value 0"]
144impl crate::Resettable for TV_IO_TRI_SPEC {
145    const RESET_VALUE: Self::Ux = 0;
146}
d1_pac/tcon_tv0/tv_io_tri.rs

d1_pac/tcon_tv0/
tv_io_tri.rs
