d1_pac/tcon_tv0/
tv_data_io_tri0.rs

1#[doc = "Register `tv_data_io_tri0` reader"]
2pub type R = crate::R<TV_DATA_IO_TRI0_SPEC>;
3#[doc = "Register `tv_data_io_tri0` writer"]
4pub type W = crate::W<TV_DATA_IO_TRI0_SPEC>;
5#[doc = "Field `g_y_ch_data_out_tri_en` reader - G Y Channel Data Output Trigger Enable"]
6pub type G_Y_CH_DATA_OUT_TRI_EN_R = crate::FieldReader<G_Y_CH_DATA_OUT_TRI_EN_A>;
7#[doc = "G Y Channel Data Output Trigger Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u16)]
10pub enum G_Y_CH_DATA_OUT_TRI_EN_A {
11    #[doc = "0: disable"]
12    DISABLE = 0,
13    #[doc = "1: enable"]
14    ENABLE = 1,
15}
16impl From<G_Y_CH_DATA_OUT_TRI_EN_A> for u16 {
17    #[inline(always)]
18    fn from(variant: G_Y_CH_DATA_OUT_TRI_EN_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for G_Y_CH_DATA_OUT_TRI_EN_A {
23    type Ux = u16;
24}
25impl G_Y_CH_DATA_OUT_TRI_EN_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<G_Y_CH_DATA_OUT_TRI_EN_A> {
29        match self.bits {
30            0 => Some(G_Y_CH_DATA_OUT_TRI_EN_A::DISABLE),
31            1 => Some(G_Y_CH_DATA_OUT_TRI_EN_A::ENABLE),
32            _ => None,
33        }
34    }
35    #[doc = "disable"]
36    #[inline(always)]
37    pub fn is_disable(&self) -> bool {
38        *self == G_Y_CH_DATA_OUT_TRI_EN_A::DISABLE
39    }
40    #[doc = "enable"]
41    #[inline(always)]
42    pub fn is_enable(&self) -> bool {
43        *self == G_Y_CH_DATA_OUT_TRI_EN_A::ENABLE
44    }
45}
46#[doc = "Field `g_y_ch_data_out_tri_en` writer - G Y Channel Data Output Trigger Enable"]
47pub type G_Y_CH_DATA_OUT_TRI_EN_W<'a, REG> =
48    crate::FieldWriter<'a, REG, 10, G_Y_CH_DATA_OUT_TRI_EN_A>;
49impl<'a, REG> G_Y_CH_DATA_OUT_TRI_EN_W<'a, REG>
50where
51    REG: crate::Writable + crate::RegisterSpec,
52    REG::Ux: From<u16>,
53{
54    #[doc = "disable"]
55    #[inline(always)]
56    pub fn disable(self) -> &'a mut crate::W<REG> {
57        self.variant(G_Y_CH_DATA_OUT_TRI_EN_A::DISABLE)
58    }
59    #[doc = "enable"]
60    #[inline(always)]
61    pub fn enable(self) -> &'a mut crate::W<REG> {
62        self.variant(G_Y_CH_DATA_OUT_TRI_EN_A::ENABLE)
63    }
64}
65#[doc = "Field `r_cb_ch_data_out_tri_en` reader - R CB Channel Data Output Trigger Enable"]
66pub type R_CB_CH_DATA_OUT_TRI_EN_R = crate::FieldReader<R_CB_CH_DATA_OUT_TRI_EN_A>;
67#[doc = "R CB Channel Data Output Trigger Enable\n\nValue on reset: 0"]
68#[derive(Clone, Copy, Debug, PartialEq, Eq)]
69#[repr(u16)]
70pub enum R_CB_CH_DATA_OUT_TRI_EN_A {
71    #[doc = "0: disable"]
72    DISABLE = 0,
73    #[doc = "1: enable"]
74    ENABLE = 1,
75}
76impl From<R_CB_CH_DATA_OUT_TRI_EN_A> for u16 {
77    #[inline(always)]
78    fn from(variant: R_CB_CH_DATA_OUT_TRI_EN_A) -> Self {
79        variant as _
80    }
81}
82impl crate::FieldSpec for R_CB_CH_DATA_OUT_TRI_EN_A {
83    type Ux = u16;
84}
85impl R_CB_CH_DATA_OUT_TRI_EN_R {
86    #[doc = "Get enumerated values variant"]
87    #[inline(always)]
88    pub const fn variant(&self) -> Option<R_CB_CH_DATA_OUT_TRI_EN_A> {
89        match self.bits {
90            0 => Some(R_CB_CH_DATA_OUT_TRI_EN_A::DISABLE),
91            1 => Some(R_CB_CH_DATA_OUT_TRI_EN_A::ENABLE),
92            _ => None,
93        }
94    }
95    #[doc = "disable"]
96    #[inline(always)]
97    pub fn is_disable(&self) -> bool {
98        *self == R_CB_CH_DATA_OUT_TRI_EN_A::DISABLE
99    }
100    #[doc = "enable"]
101    #[inline(always)]
102    pub fn is_enable(&self) -> bool {
103        *self == R_CB_CH_DATA_OUT_TRI_EN_A::ENABLE
104    }
105}
106#[doc = "Field `r_cb_ch_data_out_tri_en` writer - R CB Channel Data Output Trigger Enable"]
107pub type R_CB_CH_DATA_OUT_TRI_EN_W<'a, REG> =
108    crate::FieldWriter<'a, REG, 10, R_CB_CH_DATA_OUT_TRI_EN_A>;
109impl<'a, REG> R_CB_CH_DATA_OUT_TRI_EN_W<'a, REG>
110where
111    REG: crate::Writable + crate::RegisterSpec,
112    REG::Ux: From<u16>,
113{
114    #[doc = "disable"]
115    #[inline(always)]
116    pub fn disable(self) -> &'a mut crate::W<REG> {
117        self.variant(R_CB_CH_DATA_OUT_TRI_EN_A::DISABLE)
118    }
119    #[doc = "enable"]
120    #[inline(always)]
121    pub fn enable(self) -> &'a mut crate::W<REG> {
122        self.variant(R_CB_CH_DATA_OUT_TRI_EN_A::ENABLE)
123    }
124}
125impl R {
126    #[doc = "Bits 0:9 - G Y Channel Data Output Trigger Enable"]
127    #[inline(always)]
128    pub fn g_y_ch_data_out_tri_en(&self) -> G_Y_CH_DATA_OUT_TRI_EN_R {
129        G_Y_CH_DATA_OUT_TRI_EN_R::new((self.bits & 0x03ff) as u16)
130    }
131    #[doc = "Bits 16:25 - R CB Channel Data Output Trigger Enable"]
132    #[inline(always)]
133    pub fn r_cb_ch_data_out_tri_en(&self) -> R_CB_CH_DATA_OUT_TRI_EN_R {
134        R_CB_CH_DATA_OUT_TRI_EN_R::new(((self.bits >> 16) & 0x03ff) as u16)
135    }
136}
137impl W {
138    #[doc = "Bits 0:9 - G Y Channel Data Output Trigger Enable"]
139    #[inline(always)]
140    #[must_use]
141    pub fn g_y_ch_data_out_tri_en(&mut self) -> G_Y_CH_DATA_OUT_TRI_EN_W<TV_DATA_IO_TRI0_SPEC> {
142        G_Y_CH_DATA_OUT_TRI_EN_W::new(self, 0)
143    }
144    #[doc = "Bits 16:25 - R CB Channel Data Output Trigger Enable"]
145    #[inline(always)]
146    #[must_use]
147    pub fn r_cb_ch_data_out_tri_en(&mut self) -> R_CB_CH_DATA_OUT_TRI_EN_W<TV_DATA_IO_TRI0_SPEC> {
148        R_CB_CH_DATA_OUT_TRI_EN_W::new(self, 16)
149    }
150    #[doc = r" Writes raw bits to the register."]
151    #[doc = r""]
152    #[doc = r" # Safety"]
153    #[doc = r""]
154    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
155    #[inline(always)]
156    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
157        self.bits = bits;
158        self
159    }
160}
161#[doc = "TCON Data IO Enable Control0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tv_data_io_tri0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tv_data_io_tri0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
162pub struct TV_DATA_IO_TRI0_SPEC;
163impl crate::RegisterSpec for TV_DATA_IO_TRI0_SPEC {
164    type Ux = u32;
165}
166#[doc = "`read()` method returns [`tv_data_io_tri0::R`](R) reader structure"]
167impl crate::Readable for TV_DATA_IO_TRI0_SPEC {}
168#[doc = "`write(|w| ..)` method takes [`tv_data_io_tri0::W`](W) writer structure"]
169impl crate::Writable for TV_DATA_IO_TRI0_SPEC {
170    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
171    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
172}
173#[doc = "`reset()` method sets tv_data_io_tri0 to value 0"]
174impl crate::Resettable for TV_DATA_IO_TRI0_SPEC {
175    const RESET_VALUE: Self::Ux = 0;
176}
d1_pac/tcon_tv0/tv_data_io_tri0.rs

d1_pac/tcon_tv0/
tv_data_io_tri0.rs
