d1_pac/tcon_tv0/
tv_data_io_pol0.rs

1#[doc = "Register `tv_data_io_pol0` reader"]
2pub type R = crate::R<TV_DATA_IO_POL0_SPEC>;
3#[doc = "Register `tv_data_io_pol0` writer"]
4pub type W = crate::W<TV_DATA_IO_POL0_SPEC>;
5#[doc = "Field `g_y_ch_data_inv` reader - G Y Channel Data Inv"]
6pub type G_Y_CH_DATA_INV_R = crate::FieldReader<G_Y_CH_DATA_INV_A>;
7#[doc = "G Y Channel Data Inv\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u16)]
10pub enum G_Y_CH_DATA_INV_A {
11    #[doc = "0: normal polarity"]
12    NORMAL = 0,
13    #[doc = "1: invert the specify output"]
14    INVERT = 1,
15}
16impl From<G_Y_CH_DATA_INV_A> for u16 {
17    #[inline(always)]
18    fn from(variant: G_Y_CH_DATA_INV_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for G_Y_CH_DATA_INV_A {
23    type Ux = u16;
24}
25impl G_Y_CH_DATA_INV_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<G_Y_CH_DATA_INV_A> {
29        match self.bits {
30            0 => Some(G_Y_CH_DATA_INV_A::NORMAL),
31            1 => Some(G_Y_CH_DATA_INV_A::INVERT),
32            _ => None,
33        }
34    }
35    #[doc = "normal polarity"]
36    #[inline(always)]
37    pub fn is_normal(&self) -> bool {
38        *self == G_Y_CH_DATA_INV_A::NORMAL
39    }
40    #[doc = "invert the specify output"]
41    #[inline(always)]
42    pub fn is_invert(&self) -> bool {
43        *self == G_Y_CH_DATA_INV_A::INVERT
44    }
45}
46#[doc = "Field `g_y_ch_data_inv` writer - G Y Channel Data Inv"]
47pub type G_Y_CH_DATA_INV_W<'a, REG> = crate::FieldWriter<'a, REG, 10, G_Y_CH_DATA_INV_A>;
48impl<'a, REG> G_Y_CH_DATA_INV_W<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51    REG::Ux: From<u16>,
52{
53    #[doc = "normal polarity"]
54    #[inline(always)]
55    pub fn normal(self) -> &'a mut crate::W<REG> {
56        self.variant(G_Y_CH_DATA_INV_A::NORMAL)
57    }
58    #[doc = "invert the specify output"]
59    #[inline(always)]
60    pub fn invert(self) -> &'a mut crate::W<REG> {
61        self.variant(G_Y_CH_DATA_INV_A::INVERT)
62    }
63}
64#[doc = "Field `r_cb_ch_data_inv` reader - R CB Channel Data Inv"]
65pub type R_CB_CH_DATA_INV_R = crate::FieldReader<R_CB_CH_DATA_INV_A>;
66#[doc = "R CB Channel Data Inv\n\nValue on reset: 0"]
67#[derive(Clone, Copy, Debug, PartialEq, Eq)]
68#[repr(u16)]
69pub enum R_CB_CH_DATA_INV_A {
70    #[doc = "0: normal polarity"]
71    NORMAL = 0,
72    #[doc = "1: invert the specify output"]
73    INVERT = 1,
74}
75impl From<R_CB_CH_DATA_INV_A> for u16 {
76    #[inline(always)]
77    fn from(variant: R_CB_CH_DATA_INV_A) -> Self {
78        variant as _
79    }
80}
81impl crate::FieldSpec for R_CB_CH_DATA_INV_A {
82    type Ux = u16;
83}
84impl R_CB_CH_DATA_INV_R {
85    #[doc = "Get enumerated values variant"]
86    #[inline(always)]
87    pub const fn variant(&self) -> Option<R_CB_CH_DATA_INV_A> {
88        match self.bits {
89            0 => Some(R_CB_CH_DATA_INV_A::NORMAL),
90            1 => Some(R_CB_CH_DATA_INV_A::INVERT),
91            _ => None,
92        }
93    }
94    #[doc = "normal polarity"]
95    #[inline(always)]
96    pub fn is_normal(&self) -> bool {
97        *self == R_CB_CH_DATA_INV_A::NORMAL
98    }
99    #[doc = "invert the specify output"]
100    #[inline(always)]
101    pub fn is_invert(&self) -> bool {
102        *self == R_CB_CH_DATA_INV_A::INVERT
103    }
104}
105#[doc = "Field `r_cb_ch_data_inv` writer - R CB Channel Data Inv"]
106pub type R_CB_CH_DATA_INV_W<'a, REG> = crate::FieldWriter<'a, REG, 10, R_CB_CH_DATA_INV_A>;
107impl<'a, REG> R_CB_CH_DATA_INV_W<'a, REG>
108where
109    REG: crate::Writable + crate::RegisterSpec,
110    REG::Ux: From<u16>,
111{
112    #[doc = "normal polarity"]
113    #[inline(always)]
114    pub fn normal(self) -> &'a mut crate::W<REG> {
115        self.variant(R_CB_CH_DATA_INV_A::NORMAL)
116    }
117    #[doc = "invert the specify output"]
118    #[inline(always)]
119    pub fn invert(self) -> &'a mut crate::W<REG> {
120        self.variant(R_CB_CH_DATA_INV_A::INVERT)
121    }
122}
123impl R {
124    #[doc = "Bits 0:9 - G Y Channel Data Inv"]
125    #[inline(always)]
126    pub fn g_y_ch_data_inv(&self) -> G_Y_CH_DATA_INV_R {
127        G_Y_CH_DATA_INV_R::new((self.bits & 0x03ff) as u16)
128    }
129    #[doc = "Bits 16:25 - R CB Channel Data Inv"]
130    #[inline(always)]
131    pub fn r_cb_ch_data_inv(&self) -> R_CB_CH_DATA_INV_R {
132        R_CB_CH_DATA_INV_R::new(((self.bits >> 16) & 0x03ff) as u16)
133    }
134}
135impl W {
136    #[doc = "Bits 0:9 - G Y Channel Data Inv"]
137    #[inline(always)]
138    #[must_use]
139    pub fn g_y_ch_data_inv(&mut self) -> G_Y_CH_DATA_INV_W<TV_DATA_IO_POL0_SPEC> {
140        G_Y_CH_DATA_INV_W::new(self, 0)
141    }
142    #[doc = "Bits 16:25 - R CB Channel Data Inv"]
143    #[inline(always)]
144    #[must_use]
145    pub fn r_cb_ch_data_inv(&mut self) -> R_CB_CH_DATA_INV_W<TV_DATA_IO_POL0_SPEC> {
146        R_CB_CH_DATA_INV_W::new(self, 16)
147    }
148    #[doc = r" Writes raw bits to the register."]
149    #[doc = r""]
150    #[doc = r" # Safety"]
151    #[doc = r""]
152    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
155        self.bits = bits;
156        self
157    }
158}
159#[doc = "TCON Data IO Polarity Control0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tv_data_io_pol0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tv_data_io_pol0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
160pub struct TV_DATA_IO_POL0_SPEC;
161impl crate::RegisterSpec for TV_DATA_IO_POL0_SPEC {
162    type Ux = u32;
163}
164#[doc = "`read()` method returns [`tv_data_io_pol0::R`](R) reader structure"]
165impl crate::Readable for TV_DATA_IO_POL0_SPEC {}
166#[doc = "`write(|w| ..)` method takes [`tv_data_io_pol0::W`](W) writer structure"]
167impl crate::Writable for TV_DATA_IO_POL0_SPEC {
168    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
169    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
170}
171#[doc = "`reset()` method sets tv_data_io_pol0 to value 0"]
172impl crate::Resettable for TV_DATA_IO_POL0_SPEC {
173    const RESET_VALUE: Self::Ux = 0;
174}
d1_pac/tcon_tv0/tv_data_io_pol0.rs

d1_pac/tcon_tv0/
tv_data_io_pol0.rs
