d1_pac/tcon_tv0/
tv_ctl.rs

1#[doc = "Register `tv_ctl` reader"]
2pub type R = crate::R<TV_CTL_SPEC>;
3#[doc = "Register `tv_ctl` writer"]
4pub type W = crate::W<TV_CTL_SPEC>;
5#[doc = "Field `tv_src_sel` reader - TV Source Select\n\nNote: The priority of this bit is higher than TV_SRC_SEL(bit\\[2:0\\]) in TV_SRC_CTL_REG."]
6pub type TV_SRC_SEL_R = crate::BitReader<TV_SRC_SEL_A>;
7#[doc = "TV Source Select\n\nNote: The priority of this bit is higher than TV_SRC_SEL(bit\\[2:0\\]) in TV_SRC_CTL_REG.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TV_SRC_SEL_A {
10    #[doc = "1: BLUE data"]
11    BLUE_DATA = 1,
12}
13impl From<TV_SRC_SEL_A> for bool {
14    #[inline(always)]
15    fn from(variant: TV_SRC_SEL_A) -> Self {
16        variant as u8 != 0
17    }
18}
19impl TV_SRC_SEL_R {
20    #[doc = "Get enumerated values variant"]
21    #[inline(always)]
22    pub const fn variant(&self) -> Option<TV_SRC_SEL_A> {
23        match self.bits {
24            true => Some(TV_SRC_SEL_A::BLUE_DATA),
25            _ => None,
26        }
27    }
28    #[doc = "BLUE data"]
29    #[inline(always)]
30    pub fn is_blue_data(&self) -> bool {
31        *self == TV_SRC_SEL_A::BLUE_DATA
32    }
33}
34#[doc = "Field `tv_src_sel` writer - TV Source Select\n\nNote: The priority of this bit is higher than TV_SRC_SEL(bit\\[2:0\\]) in TV_SRC_CTL_REG."]
35pub type TV_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG, TV_SRC_SEL_A>;
36impl<'a, REG> TV_SRC_SEL_W<'a, REG>
37where
38    REG: crate::Writable + crate::RegisterSpec,
39{
40    #[doc = "BLUE data"]
41    #[inline(always)]
42    pub fn blue_data(self) -> &'a mut crate::W<REG> {
43        self.variant(TV_SRC_SEL_A::BLUE_DATA)
44    }
45}
46#[doc = "Field `start_delay` reader - This is for DE0 and DE1."]
47pub type START_DELAY_R = crate::FieldReader;
48#[doc = "Field `start_delay` writer - This is for DE0 and DE1."]
49pub type START_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
50#[doc = "Field `tv_en` reader - When enable TCON_TV, this bit and the 0x0000\\[bit31\\] need to be enabled."]
51pub type TV_EN_R = crate::BitReader<TV_EN_A>;
52#[doc = "When enable TCON_TV, this bit and the 0x0000\\[bit31\\] need to be enabled.\n\nValue on reset: 0"]
53#[derive(Clone, Copy, Debug, PartialEq, Eq)]
54pub enum TV_EN_A {
55    #[doc = "0: Disable"]
56    DISABLE = 0,
57    #[doc = "1: Enable"]
58    ENABLE = 1,
59}
60impl From<TV_EN_A> for bool {
61    #[inline(always)]
62    fn from(variant: TV_EN_A) -> Self {
63        variant as u8 != 0
64    }
65}
66impl TV_EN_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub const fn variant(&self) -> TV_EN_A {
70        match self.bits {
71            false => TV_EN_A::DISABLE,
72            true => TV_EN_A::ENABLE,
73        }
74    }
75    #[doc = "Disable"]
76    #[inline(always)]
77    pub fn is_disable(&self) -> bool {
78        *self == TV_EN_A::DISABLE
79    }
80    #[doc = "Enable"]
81    #[inline(always)]
82    pub fn is_enable(&self) -> bool {
83        *self == TV_EN_A::ENABLE
84    }
85}
86#[doc = "Field `tv_en` writer - When enable TCON_TV, this bit and the 0x0000\\[bit31\\] need to be enabled."]
87pub type TV_EN_W<'a, REG> = crate::BitWriter<'a, REG, TV_EN_A>;
88impl<'a, REG> TV_EN_W<'a, REG>
89where
90    REG: crate::Writable + crate::RegisterSpec,
91{
92    #[doc = "Disable"]
93    #[inline(always)]
94    pub fn disable(self) -> &'a mut crate::W<REG> {
95        self.variant(TV_EN_A::DISABLE)
96    }
97    #[doc = "Enable"]
98    #[inline(always)]
99    pub fn enable(self) -> &'a mut crate::W<REG> {
100        self.variant(TV_EN_A::ENABLE)
101    }
102}
103impl R {
104    #[doc = "Bit 1 - TV Source Select\n\nNote: The priority of this bit is higher than TV_SRC_SEL(bit\\[2:0\\]) in TV_SRC_CTL_REG."]
105    #[inline(always)]
106    pub fn tv_src_sel(&self) -> TV_SRC_SEL_R {
107        TV_SRC_SEL_R::new(((self.bits >> 1) & 1) != 0)
108    }
109    #[doc = "Bits 4:8 - This is for DE0 and DE1."]
110    #[inline(always)]
111    pub fn start_delay(&self) -> START_DELAY_R {
112        START_DELAY_R::new(((self.bits >> 4) & 0x1f) as u8)
113    }
114    #[doc = "Bit 31 - When enable TCON_TV, this bit and the 0x0000\\[bit31\\] need to be enabled."]
115    #[inline(always)]
116    pub fn tv_en(&self) -> TV_EN_R {
117        TV_EN_R::new(((self.bits >> 31) & 1) != 0)
118    }
119}
120impl W {
121    #[doc = "Bit 1 - TV Source Select\n\nNote: The priority of this bit is higher than TV_SRC_SEL(bit\\[2:0\\]) in TV_SRC_CTL_REG."]
122    #[inline(always)]
123    #[must_use]
124    pub fn tv_src_sel(&mut self) -> TV_SRC_SEL_W<TV_CTL_SPEC> {
125        TV_SRC_SEL_W::new(self, 1)
126    }
127    #[doc = "Bits 4:8 - This is for DE0 and DE1."]
128    #[inline(always)]
129    #[must_use]
130    pub fn start_delay(&mut self) -> START_DELAY_W<TV_CTL_SPEC> {
131        START_DELAY_W::new(self, 4)
132    }
133    #[doc = "Bit 31 - When enable TCON_TV, this bit and the 0x0000\\[bit31\\] need to be enabled."]
134    #[inline(always)]
135    #[must_use]
136    pub fn tv_en(&mut self) -> TV_EN_W<TV_CTL_SPEC> {
137        TV_EN_W::new(self, 31)
138    }
139    #[doc = r" Writes raw bits to the register."]
140    #[doc = r""]
141    #[doc = r" # Safety"]
142    #[doc = r""]
143    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
144    #[inline(always)]
145    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
146        self.bits = bits;
147        self
148    }
149}
150#[doc = "TV Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tv_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tv_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
151pub struct TV_CTL_SPEC;
152impl crate::RegisterSpec for TV_CTL_SPEC {
153    type Ux = u32;
154}
155#[doc = "`read()` method returns [`tv_ctl::R`](R) reader structure"]
156impl crate::Readable for TV_CTL_SPEC {}
157#[doc = "`write(|w| ..)` method takes [`tv_ctl::W`](W) writer structure"]
158impl crate::Writable for TV_CTL_SPEC {
159    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
160    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
161}
162#[doc = "`reset()` method sets tv_ctl to value 0"]
163impl crate::Resettable for TV_CTL_SPEC {
164    const RESET_VALUE: Self::Ux = 0;
165}
d1_pac/tcon_tv0/tv_ctl.rs

d1_pac/tcon_tv0/
tv_ctl.rs
