d1_pac/tcon_lcd0/
lcd_io_tri.rs

1#[doc = "Register `lcd_io_tri` reader"]
2pub type R = crate::R<LCD_IO_TRI_SPEC>;
3#[doc = "Register `lcd_io_tri` writer"]
4pub type W = crate::W<LCD_IO_TRI_SPEC>;
5#[doc = "Field `data_output_tri_en` reader - LCD output port D\\[23:0\\] output enable, with independent bit control."]
6pub type DATA_OUTPUT_TRI_EN_R = crate::FieldReader<u32>;
7#[doc = "Field `data_output_tri_en` writer - LCD output port D\\[23:0\\] output enable, with independent bit control."]
8pub type DATA_OUTPUT_TRI_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
9#[doc = "Field `io_output_tri_en[0-3]` reader - Enable the output of IO\\[i\\]"]
10pub type IO_OUTPUT_TRI_EN_R = crate::BitReader<IO_OUTPUT_TRI_EN_A>;
11#[doc = "Enable the output of IO\\[i\\]\n\nValue on reset: 1"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum IO_OUTPUT_TRI_EN_A {
14    #[doc = "1: Disable"]
15    DISABLE = 1,
16    #[doc = "0: Enable"]
17    ENABLE = 0,
18}
19impl From<IO_OUTPUT_TRI_EN_A> for bool {
20    #[inline(always)]
21    fn from(variant: IO_OUTPUT_TRI_EN_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl IO_OUTPUT_TRI_EN_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> IO_OUTPUT_TRI_EN_A {
29        match self.bits {
30            true => IO_OUTPUT_TRI_EN_A::DISABLE,
31            false => IO_OUTPUT_TRI_EN_A::ENABLE,
32        }
33    }
34    #[doc = "Disable"]
35    #[inline(always)]
36    pub fn is_disable(&self) -> bool {
37        *self == IO_OUTPUT_TRI_EN_A::DISABLE
38    }
39    #[doc = "Enable"]
40    #[inline(always)]
41    pub fn is_enable(&self) -> bool {
42        *self == IO_OUTPUT_TRI_EN_A::ENABLE
43    }
44}
45#[doc = "Field `io_output_tri_en[0-3]` writer - Enable the output of IO\\[i\\]"]
46pub type IO_OUTPUT_TRI_EN_W<'a, REG> = crate::BitWriter<'a, REG, IO_OUTPUT_TRI_EN_A>;
47impl<'a, REG> IO_OUTPUT_TRI_EN_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Disable"]
52    #[inline(always)]
53    pub fn disable(self) -> &'a mut crate::W<REG> {
54        self.variant(IO_OUTPUT_TRI_EN_A::DISABLE)
55    }
56    #[doc = "Enable"]
57    #[inline(always)]
58    pub fn enable(self) -> &'a mut crate::W<REG> {
59        self.variant(IO_OUTPUT_TRI_EN_A::ENABLE)
60    }
61}
62#[doc = "Field `rgb_endian` reader - Set the endian of data bits"]
63pub type RGB_ENDIAN_R = crate::BitReader<RGB_ENDIAN_A>;
64#[doc = "Set the endian of data bits\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum RGB_ENDIAN_A {
67    #[doc = "0: Normal"]
68    NORMAL = 0,
69    #[doc = "1: Bits_invert"]
70    B_ITS_INVERT = 1,
71}
72impl From<RGB_ENDIAN_A> for bool {
73    #[inline(always)]
74    fn from(variant: RGB_ENDIAN_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl RGB_ENDIAN_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> RGB_ENDIAN_A {
82        match self.bits {
83            false => RGB_ENDIAN_A::NORMAL,
84            true => RGB_ENDIAN_A::B_ITS_INVERT,
85        }
86    }
87    #[doc = "Normal"]
88    #[inline(always)]
89    pub fn is_normal(&self) -> bool {
90        *self == RGB_ENDIAN_A::NORMAL
91    }
92    #[doc = "Bits_invert"]
93    #[inline(always)]
94    pub fn is_b_its_invert(&self) -> bool {
95        *self == RGB_ENDIAN_A::B_ITS_INVERT
96    }
97}
98#[doc = "Field `rgb_endian` writer - Set the endian of data bits"]
99pub type RGB_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG, RGB_ENDIAN_A>;
100impl<'a, REG> RGB_ENDIAN_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "Normal"]
105    #[inline(always)]
106    pub fn normal(self) -> &'a mut crate::W<REG> {
107        self.variant(RGB_ENDIAN_A::NORMAL)
108    }
109    #[doc = "Bits_invert"]
110    #[inline(always)]
111    pub fn b_its_invert(self) -> &'a mut crate::W<REG> {
112        self.variant(RGB_ENDIAN_A::B_ITS_INVERT)
113    }
114}
115impl R {
116    #[doc = "Bits 0:23 - LCD output port D\\[23:0\\] output enable, with independent bit control."]
117    #[inline(always)]
118    pub fn data_output_tri_en(&self) -> DATA_OUTPUT_TRI_EN_R {
119        DATA_OUTPUT_TRI_EN_R::new(self.bits & 0x00ff_ffff)
120    }
121    #[doc = "Enable the output of IO\\[i\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `io0_output_tri_en` field"]
122    #[inline(always)]
123    pub fn io_output_tri_en(&self, n: u8) -> IO_OUTPUT_TRI_EN_R {
124        #[allow(clippy::no_effect)]
125        [(); 4][n as usize];
126        IO_OUTPUT_TRI_EN_R::new(((self.bits >> (n + 24)) & 1) != 0)
127    }
128    #[doc = "Bit 24 - Enable the output of IO\\[i\\]"]
129    #[inline(always)]
130    pub fn io0_output_tri_en(&self) -> IO_OUTPUT_TRI_EN_R {
131        IO_OUTPUT_TRI_EN_R::new(((self.bits >> 24) & 1) != 0)
132    }
133    #[doc = "Bit 25 - Enable the output of IO\\[i\\]"]
134    #[inline(always)]
135    pub fn io1_output_tri_en(&self) -> IO_OUTPUT_TRI_EN_R {
136        IO_OUTPUT_TRI_EN_R::new(((self.bits >> 25) & 1) != 0)
137    }
138    #[doc = "Bit 26 - Enable the output of IO\\[i\\]"]
139    #[inline(always)]
140    pub fn io2_output_tri_en(&self) -> IO_OUTPUT_TRI_EN_R {
141        IO_OUTPUT_TRI_EN_R::new(((self.bits >> 26) & 1) != 0)
142    }
143    #[doc = "Bit 27 - Enable the output of IO\\[i\\]"]
144    #[inline(always)]
145    pub fn io3_output_tri_en(&self) -> IO_OUTPUT_TRI_EN_R {
146        IO_OUTPUT_TRI_EN_R::new(((self.bits >> 27) & 1) != 0)
147    }
148    #[doc = "Bit 28 - Set the endian of data bits"]
149    #[inline(always)]
150    pub fn rgb_endian(&self) -> RGB_ENDIAN_R {
151        RGB_ENDIAN_R::new(((self.bits >> 28) & 1) != 0)
152    }
153}
154impl W {
155    #[doc = "Bits 0:23 - LCD output port D\\[23:0\\] output enable, with independent bit control."]
156    #[inline(always)]
157    #[must_use]
158    pub fn data_output_tri_en(&mut self) -> DATA_OUTPUT_TRI_EN_W<LCD_IO_TRI_SPEC> {
159        DATA_OUTPUT_TRI_EN_W::new(self, 0)
160    }
161    #[doc = "Enable the output of IO\\[i\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `io0_output_tri_en` field"]
162    #[inline(always)]
163    #[must_use]
164    pub fn io_output_tri_en(&mut self, n: u8) -> IO_OUTPUT_TRI_EN_W<LCD_IO_TRI_SPEC> {
165        #[allow(clippy::no_effect)]
166        [(); 4][n as usize];
167        IO_OUTPUT_TRI_EN_W::new(self, n + 24)
168    }
169    #[doc = "Bit 24 - Enable the output of IO\\[i\\]"]
170    #[inline(always)]
171    #[must_use]
172    pub fn io0_output_tri_en(&mut self) -> IO_OUTPUT_TRI_EN_W<LCD_IO_TRI_SPEC> {
173        IO_OUTPUT_TRI_EN_W::new(self, 24)
174    }
175    #[doc = "Bit 25 - Enable the output of IO\\[i\\]"]
176    #[inline(always)]
177    #[must_use]
178    pub fn io1_output_tri_en(&mut self) -> IO_OUTPUT_TRI_EN_W<LCD_IO_TRI_SPEC> {
179        IO_OUTPUT_TRI_EN_W::new(self, 25)
180    }
181    #[doc = "Bit 26 - Enable the output of IO\\[i\\]"]
182    #[inline(always)]
183    #[must_use]
184    pub fn io2_output_tri_en(&mut self) -> IO_OUTPUT_TRI_EN_W<LCD_IO_TRI_SPEC> {
185        IO_OUTPUT_TRI_EN_W::new(self, 26)
186    }
187    #[doc = "Bit 27 - Enable the output of IO\\[i\\]"]
188    #[inline(always)]
189    #[must_use]
190    pub fn io3_output_tri_en(&mut self) -> IO_OUTPUT_TRI_EN_W<LCD_IO_TRI_SPEC> {
191        IO_OUTPUT_TRI_EN_W::new(self, 27)
192    }
193    #[doc = "Bit 28 - Set the endian of data bits"]
194    #[inline(always)]
195    #[must_use]
196    pub fn rgb_endian(&mut self) -> RGB_ENDIAN_W<LCD_IO_TRI_SPEC> {
197        RGB_ENDIAN_W::new(self, 28)
198    }
199    #[doc = r" Writes raw bits to the register."]
200    #[doc = r""]
201    #[doc = r" # Safety"]
202    #[doc = r""]
203    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
204    #[inline(always)]
205    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
206        self.bits = bits;
207        self
208    }
209}
210#[doc = "LCD IO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_io_tri::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_io_tri::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
211pub struct LCD_IO_TRI_SPEC;
212impl crate::RegisterSpec for LCD_IO_TRI_SPEC {
213    type Ux = u32;
214}
215#[doc = "`read()` method returns [`lcd_io_tri::R`](R) reader structure"]
216impl crate::Readable for LCD_IO_TRI_SPEC {}
217#[doc = "`write(|w| ..)` method takes [`lcd_io_tri::W`](W) writer structure"]
218impl crate::Writable for LCD_IO_TRI_SPEC {
219    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
220    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
221}
222#[doc = "`reset()` method sets lcd_io_tri to value 0x0fff_ffff"]
223impl crate::Resettable for LCD_IO_TRI_SPEC {
224    const RESET_VALUE: Self::Ux = 0x0fff_ffff;
225}
d1_pac/tcon_lcd0/lcd_io_tri.rs

d1_pac/tcon_lcd0/
lcd_io_tri.rs
