d1_pac/tcon_lcd0/
lcd_io_pol.rs

1#[doc = "Register `lcd_io_pol` reader"]
2pub type R = crate::R<LCD_IO_POL_SPEC>;
3#[doc = "Register `lcd_io_pol` writer"]
4pub type W = crate::W<LCD_IO_POL_SPEC>;
5#[doc = "Field `data_inv` reader - LCD output port D\\[23:0\\] polarity control, with independent bit control."]
6pub type DATA_INV_R = crate::FieldReader<u32>;
7#[doc = "Field `data_inv` writer - LCD output port D\\[23:0\\] polarity control, with independent bit control."]
8pub type DATA_INV_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
9#[doc = "Field `io_inv[0-3]` reader - Enable invert function of IO\\[i\\]"]
10pub type IO_INV_R = crate::BitReader<IO_INV_A>;
11#[doc = "Enable invert function of IO\\[i\\]\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum IO_INV_A {
14    #[doc = "0: Not invert"]
15    NOT_INVERT = 0,
16    #[doc = "1: Invert"]
17    INVERT = 1,
18}
19impl From<IO_INV_A> for bool {
20    #[inline(always)]
21    fn from(variant: IO_INV_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl IO_INV_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> IO_INV_A {
29        match self.bits {
30            false => IO_INV_A::NOT_INVERT,
31            true => IO_INV_A::INVERT,
32        }
33    }
34    #[doc = "Not invert"]
35    #[inline(always)]
36    pub fn is_not_invert(&self) -> bool {
37        *self == IO_INV_A::NOT_INVERT
38    }
39    #[doc = "Invert"]
40    #[inline(always)]
41    pub fn is_invert(&self) -> bool {
42        *self == IO_INV_A::INVERT
43    }
44}
45#[doc = "Field `io_inv[0-3]` writer - Enable invert function of IO\\[i\\]"]
46pub type IO_INV_W<'a, REG> = crate::BitWriter<'a, REG, IO_INV_A>;
47impl<'a, REG> IO_INV_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Not invert"]
52    #[inline(always)]
53    pub fn not_invert(self) -> &'a mut crate::W<REG> {
54        self.variant(IO_INV_A::NOT_INVERT)
55    }
56    #[doc = "Invert"]
57    #[inline(always)]
58    pub fn invert(self) -> &'a mut crate::W<REG> {
59        self.variant(IO_INV_A::INVERT)
60    }
61}
62#[doc = "Field `dclk_sel` reader - Set the phase offset of clock and data in hv mode."]
63pub type DCLK_SEL_R = crate::FieldReader<DCLK_SEL_A>;
64#[doc = "Set the phase offset of clock and data in hv mode.\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum DCLK_SEL_A {
68    #[doc = "0: Used DCLK0 (normal phase offset)"]
69    DCLK0 = 0,
70    #[doc = "1: Used DCLK1 (1/3 phase offset)"]
71    DCLK1 = 1,
72    #[doc = "2: Used DCLK2 (2/3 phase offset)"]
73    DCLK2 = 2,
74    #[doc = "4: DCLK0/2 phase 0"]
75    DCLK02_0 = 4,
76    #[doc = "5: DCLK0/2 phase 90"]
77    DCLK02_90 = 5,
78}
79impl From<DCLK_SEL_A> for u8 {
80    #[inline(always)]
81    fn from(variant: DCLK_SEL_A) -> Self {
82        variant as _
83    }
84}
85impl crate::FieldSpec for DCLK_SEL_A {
86    type Ux = u8;
87}
88impl DCLK_SEL_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Option<DCLK_SEL_A> {
92        match self.bits {
93            0 => Some(DCLK_SEL_A::DCLK0),
94            1 => Some(DCLK_SEL_A::DCLK1),
95            2 => Some(DCLK_SEL_A::DCLK2),
96            4 => Some(DCLK_SEL_A::DCLK02_0),
97            5 => Some(DCLK_SEL_A::DCLK02_90),
98            _ => None,
99        }
100    }
101    #[doc = "Used DCLK0 (normal phase offset)"]
102    #[inline(always)]
103    pub fn is_dclk0(&self) -> bool {
104        *self == DCLK_SEL_A::DCLK0
105    }
106    #[doc = "Used DCLK1 (1/3 phase offset)"]
107    #[inline(always)]
108    pub fn is_dclk1(&self) -> bool {
109        *self == DCLK_SEL_A::DCLK1
110    }
111    #[doc = "Used DCLK2 (2/3 phase offset)"]
112    #[inline(always)]
113    pub fn is_dclk2(&self) -> bool {
114        *self == DCLK_SEL_A::DCLK2
115    }
116    #[doc = "DCLK0/2 phase 0"]
117    #[inline(always)]
118    pub fn is_dclk02_0(&self) -> bool {
119        *self == DCLK_SEL_A::DCLK02_0
120    }
121    #[doc = "DCLK0/2 phase 90"]
122    #[inline(always)]
123    pub fn is_dclk02_90(&self) -> bool {
124        *self == DCLK_SEL_A::DCLK02_90
125    }
126}
127#[doc = "Field `dclk_sel` writer - Set the phase offset of clock and data in hv mode."]
128pub type DCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, DCLK_SEL_A>;
129impl<'a, REG> DCLK_SEL_W<'a, REG>
130where
131    REG: crate::Writable + crate::RegisterSpec,
132    REG::Ux: From<u8>,
133{
134    #[doc = "Used DCLK0 (normal phase offset)"]
135    #[inline(always)]
136    pub fn dclk0(self) -> &'a mut crate::W<REG> {
137        self.variant(DCLK_SEL_A::DCLK0)
138    }
139    #[doc = "Used DCLK1 (1/3 phase offset)"]
140    #[inline(always)]
141    pub fn dclk1(self) -> &'a mut crate::W<REG> {
142        self.variant(DCLK_SEL_A::DCLK1)
143    }
144    #[doc = "Used DCLK2 (2/3 phase offset)"]
145    #[inline(always)]
146    pub fn dclk2(self) -> &'a mut crate::W<REG> {
147        self.variant(DCLK_SEL_A::DCLK2)
148    }
149    #[doc = "DCLK0/2 phase 0"]
150    #[inline(always)]
151    pub fn dclk02_0(self) -> &'a mut crate::W<REG> {
152        self.variant(DCLK_SEL_A::DCLK02_0)
153    }
154    #[doc = "DCLK0/2 phase 90"]
155    #[inline(always)]
156    pub fn dclk02_90(self) -> &'a mut crate::W<REG> {
157        self.variant(DCLK_SEL_A::DCLK02_90)
158    }
159}
160#[doc = "Field `io_output_sel` reader - When it is set as '1', the d\\[23:0\\], io0, io1, io3 are sync to dclk."]
161pub type IO_OUTPUT_SEL_R = crate::BitReader<IO_OUTPUT_SEL_A>;
162#[doc = "When it is set as '1', the d\\[23:0\\], io0, io1, io3 are sync to dclk.\n\nValue on reset: 0"]
163#[derive(Clone, Copy, Debug, PartialEq, Eq)]
164pub enum IO_OUTPUT_SEL_A {
165    #[doc = "0: Normal output"]
166    NORMAL = 0,
167    #[doc = "1: Register output"]
168    R_EGISTER = 1,
169}
170impl From<IO_OUTPUT_SEL_A> for bool {
171    #[inline(always)]
172    fn from(variant: IO_OUTPUT_SEL_A) -> Self {
173        variant as u8 != 0
174    }
175}
176impl IO_OUTPUT_SEL_R {
177    #[doc = "Get enumerated values variant"]
178    #[inline(always)]
179    pub const fn variant(&self) -> IO_OUTPUT_SEL_A {
180        match self.bits {
181            false => IO_OUTPUT_SEL_A::NORMAL,
182            true => IO_OUTPUT_SEL_A::R_EGISTER,
183        }
184    }
185    #[doc = "Normal output"]
186    #[inline(always)]
187    pub fn is_normal(&self) -> bool {
188        *self == IO_OUTPUT_SEL_A::NORMAL
189    }
190    #[doc = "Register output"]
191    #[inline(always)]
192    pub fn is_r_egister(&self) -> bool {
193        *self == IO_OUTPUT_SEL_A::R_EGISTER
194    }
195}
196#[doc = "Field `io_output_sel` writer - When it is set as '1', the d\\[23:0\\], io0, io1, io3 are sync to dclk."]
197pub type IO_OUTPUT_SEL_W<'a, REG> = crate::BitWriter<'a, REG, IO_OUTPUT_SEL_A>;
198impl<'a, REG> IO_OUTPUT_SEL_W<'a, REG>
199where
200    REG: crate::Writable + crate::RegisterSpec,
201{
202    #[doc = "Normal output"]
203    #[inline(always)]
204    pub fn normal(self) -> &'a mut crate::W<REG> {
205        self.variant(IO_OUTPUT_SEL_A::NORMAL)
206    }
207    #[doc = "Register output"]
208    #[inline(always)]
209    pub fn r_egister(self) -> &'a mut crate::W<REG> {
210        self.variant(IO_OUTPUT_SEL_A::R_EGISTER)
211    }
212}
213impl R {
214    #[doc = "Bits 0:23 - LCD output port D\\[23:0\\] polarity control, with independent bit control."]
215    #[inline(always)]
216    pub fn data_inv(&self) -> DATA_INV_R {
217        DATA_INV_R::new(self.bits & 0x00ff_ffff)
218    }
219    #[doc = "Enable invert function of IO\\[i\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `io0_inv` field"]
220    #[inline(always)]
221    pub fn io_inv(&self, n: u8) -> IO_INV_R {
222        #[allow(clippy::no_effect)]
223        [(); 4][n as usize];
224        IO_INV_R::new(((self.bits >> (n + 24)) & 1) != 0)
225    }
226    #[doc = "Bit 24 - Enable invert function of IO\\[i\\]"]
227    #[inline(always)]
228    pub fn io0_inv(&self) -> IO_INV_R {
229        IO_INV_R::new(((self.bits >> 24) & 1) != 0)
230    }
231    #[doc = "Bit 25 - Enable invert function of IO\\[i\\]"]
232    #[inline(always)]
233    pub fn io1_inv(&self) -> IO_INV_R {
234        IO_INV_R::new(((self.bits >> 25) & 1) != 0)
235    }
236    #[doc = "Bit 26 - Enable invert function of IO\\[i\\]"]
237    #[inline(always)]
238    pub fn io2_inv(&self) -> IO_INV_R {
239        IO_INV_R::new(((self.bits >> 26) & 1) != 0)
240    }
241    #[doc = "Bit 27 - Enable invert function of IO\\[i\\]"]
242    #[inline(always)]
243    pub fn io3_inv(&self) -> IO_INV_R {
244        IO_INV_R::new(((self.bits >> 27) & 1) != 0)
245    }
246    #[doc = "Bits 28:30 - Set the phase offset of clock and data in hv mode."]
247    #[inline(always)]
248    pub fn dclk_sel(&self) -> DCLK_SEL_R {
249        DCLK_SEL_R::new(((self.bits >> 28) & 7) as u8)
250    }
251    #[doc = "Bit 31 - When it is set as '1', the d\\[23:0\\], io0, io1, io3 are sync to dclk."]
252    #[inline(always)]
253    pub fn io_output_sel(&self) -> IO_OUTPUT_SEL_R {
254        IO_OUTPUT_SEL_R::new(((self.bits >> 31) & 1) != 0)
255    }
256}
257impl W {
258    #[doc = "Bits 0:23 - LCD output port D\\[23:0\\] polarity control, with independent bit control."]
259    #[inline(always)]
260    #[must_use]
261    pub fn data_inv(&mut self) -> DATA_INV_W<LCD_IO_POL_SPEC> {
262        DATA_INV_W::new(self, 0)
263    }
264    #[doc = "Enable invert function of IO\\[i\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `io0_inv` field"]
265    #[inline(always)]
266    #[must_use]
267    pub fn io_inv(&mut self, n: u8) -> IO_INV_W<LCD_IO_POL_SPEC> {
268        #[allow(clippy::no_effect)]
269        [(); 4][n as usize];
270        IO_INV_W::new(self, n + 24)
271    }
272    #[doc = "Bit 24 - Enable invert function of IO\\[i\\]"]
273    #[inline(always)]
274    #[must_use]
275    pub fn io0_inv(&mut self) -> IO_INV_W<LCD_IO_POL_SPEC> {
276        IO_INV_W::new(self, 24)
277    }
278    #[doc = "Bit 25 - Enable invert function of IO\\[i\\]"]
279    #[inline(always)]
280    #[must_use]
281    pub fn io1_inv(&mut self) -> IO_INV_W<LCD_IO_POL_SPEC> {
282        IO_INV_W::new(self, 25)
283    }
284    #[doc = "Bit 26 - Enable invert function of IO\\[i\\]"]
285    #[inline(always)]
286    #[must_use]
287    pub fn io2_inv(&mut self) -> IO_INV_W<LCD_IO_POL_SPEC> {
288        IO_INV_W::new(self, 26)
289    }
290    #[doc = "Bit 27 - Enable invert function of IO\\[i\\]"]
291    #[inline(always)]
292    #[must_use]
293    pub fn io3_inv(&mut self) -> IO_INV_W<LCD_IO_POL_SPEC> {
294        IO_INV_W::new(self, 27)
295    }
296    #[doc = "Bits 28:30 - Set the phase offset of clock and data in hv mode."]
297    #[inline(always)]
298    #[must_use]
299    pub fn dclk_sel(&mut self) -> DCLK_SEL_W<LCD_IO_POL_SPEC> {
300        DCLK_SEL_W::new(self, 28)
301    }
302    #[doc = "Bit 31 - When it is set as '1', the d\\[23:0\\], io0, io1, io3 are sync to dclk."]
303    #[inline(always)]
304    #[must_use]
305    pub fn io_output_sel(&mut self) -> IO_OUTPUT_SEL_W<LCD_IO_POL_SPEC> {
306        IO_OUTPUT_SEL_W::new(self, 31)
307    }
308    #[doc = r" Writes raw bits to the register."]
309    #[doc = r""]
310    #[doc = r" # Safety"]
311    #[doc = r""]
312    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
313    #[inline(always)]
314    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
315        self.bits = bits;
316        self
317    }
318}
319#[doc = "LCD IO Polarity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_io_pol::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_io_pol::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
320pub struct LCD_IO_POL_SPEC;
321impl crate::RegisterSpec for LCD_IO_POL_SPEC {
322    type Ux = u32;
323}
324#[doc = "`read()` method returns [`lcd_io_pol::R`](R) reader structure"]
325impl crate::Readable for LCD_IO_POL_SPEC {}
326#[doc = "`write(|w| ..)` method takes [`lcd_io_pol::W`](W) writer structure"]
327impl crate::Writable for LCD_IO_POL_SPEC {
328    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
329    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
330}
331#[doc = "`reset()` method sets lcd_io_pol to value 0"]
332impl crate::Resettable for LCD_IO_POL_SPEC {
333    const RESET_VALUE: Self::Ux = 0;
334}
d1_pac/tcon_lcd0/lcd_io_pol.rs

d1_pac/tcon_lcd0/
lcd_io_pol.rs
