d1_pac/tcon_lcd0/
lcd_hv_if.rs

1#[doc = "Register `lcd_hv_if` reader"]
2pub type R = crate::R<LCD_HV_IF_SPEC>;
3#[doc = "Register `lcd_hv_if` writer"]
4pub type W = crate::W<LCD_HV_IF_SPEC>;
5#[doc = "Field `ccir_csc_dis` reader - LCD convert source from RGB to YUV.\n\nOnly valid when HV mode is “1100”."]
6pub type CCIR_CSC_DIS_R = crate::BitReader<CCIR_CSC_DIS_A>;
7#[doc = "LCD convert source from RGB to YUV.\n\nOnly valid when HV mode is “1100”.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CCIR_CSC_DIS_A {
10    #[doc = "0: Enable"]
11    ENABLE = 0,
12    #[doc = "1: Disable"]
13    DISABLE = 1,
14}
15impl From<CCIR_CSC_DIS_A> for bool {
16    #[inline(always)]
17    fn from(variant: CCIR_CSC_DIS_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CCIR_CSC_DIS_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CCIR_CSC_DIS_A {
25        match self.bits {
26            false => CCIR_CSC_DIS_A::ENABLE,
27            true => CCIR_CSC_DIS_A::DISABLE,
28        }
29    }
30    #[doc = "Enable"]
31    #[inline(always)]
32    pub fn is_enable(&self) -> bool {
33        *self == CCIR_CSC_DIS_A::ENABLE
34    }
35    #[doc = "Disable"]
36    #[inline(always)]
37    pub fn is_disable(&self) -> bool {
38        *self == CCIR_CSC_DIS_A::DISABLE
39    }
40}
41#[doc = "Field `ccir_csc_dis` writer - LCD convert source from RGB to YUV.\n\nOnly valid when HV mode is “1100”."]
42pub type CCIR_CSC_DIS_W<'a, REG> = crate::BitWriter<'a, REG, CCIR_CSC_DIS_A>;
43impl<'a, REG> CCIR_CSC_DIS_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Enable"]
48    #[inline(always)]
49    pub fn enable(self) -> &'a mut crate::W<REG> {
50        self.variant(CCIR_CSC_DIS_A::ENABLE)
51    }
52    #[doc = "Disable"]
53    #[inline(always)]
54    pub fn disable(self) -> &'a mut crate::W<REG> {
55        self.variant(CCIR_CSC_DIS_A::DISABLE)
56    }
57}
58#[doc = "Field `yuv_eav_sav_f_line_dly` reader - Set the delay line mode."]
59pub type YUV_EAV_SAV_F_LINE_DLY_R = crate::FieldReader<YUV_EAV_SAV_F_LINE_DLY_A>;
60#[doc = "Set the delay line mode.\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u8)]
63pub enum YUV_EAV_SAV_F_LINE_DLY_A {
64    #[doc = "0: F toggle right after active video line"]
65    F_TOGGLE = 0,
66    #[doc = "1: delay 2 line (CCIR PAL)"]
67    CCIR_PAL = 1,
68    #[doc = "2: delay 3 line (CCIR NTSC)"]
69    CCIR_NTSC = 2,
70}
71impl From<YUV_EAV_SAV_F_LINE_DLY_A> for u8 {
72    #[inline(always)]
73    fn from(variant: YUV_EAV_SAV_F_LINE_DLY_A) -> Self {
74        variant as _
75    }
76}
77impl crate::FieldSpec for YUV_EAV_SAV_F_LINE_DLY_A {
78    type Ux = u8;
79}
80impl YUV_EAV_SAV_F_LINE_DLY_R {
81    #[doc = "Get enumerated values variant"]
82    #[inline(always)]
83    pub const fn variant(&self) -> Option<YUV_EAV_SAV_F_LINE_DLY_A> {
84        match self.bits {
85            0 => Some(YUV_EAV_SAV_F_LINE_DLY_A::F_TOGGLE),
86            1 => Some(YUV_EAV_SAV_F_LINE_DLY_A::CCIR_PAL),
87            2 => Some(YUV_EAV_SAV_F_LINE_DLY_A::CCIR_NTSC),
88            _ => None,
89        }
90    }
91    #[doc = "F toggle right after active video line"]
92    #[inline(always)]
93    pub fn is_f_toggle(&self) -> bool {
94        *self == YUV_EAV_SAV_F_LINE_DLY_A::F_TOGGLE
95    }
96    #[doc = "delay 2 line (CCIR PAL)"]
97    #[inline(always)]
98    pub fn is_ccir_pal(&self) -> bool {
99        *self == YUV_EAV_SAV_F_LINE_DLY_A::CCIR_PAL
100    }
101    #[doc = "delay 3 line (CCIR NTSC)"]
102    #[inline(always)]
103    pub fn is_ccir_ntsc(&self) -> bool {
104        *self == YUV_EAV_SAV_F_LINE_DLY_A::CCIR_NTSC
105    }
106}
107#[doc = "Field `yuv_eav_sav_f_line_dly` writer - Set the delay line mode."]
108pub type YUV_EAV_SAV_F_LINE_DLY_W<'a, REG> =
109    crate::FieldWriter<'a, REG, 2, YUV_EAV_SAV_F_LINE_DLY_A>;
110impl<'a, REG> YUV_EAV_SAV_F_LINE_DLY_W<'a, REG>
111where
112    REG: crate::Writable + crate::RegisterSpec,
113    REG::Ux: From<u8>,
114{
115    #[doc = "F toggle right after active video line"]
116    #[inline(always)]
117    pub fn f_toggle(self) -> &'a mut crate::W<REG> {
118        self.variant(YUV_EAV_SAV_F_LINE_DLY_A::F_TOGGLE)
119    }
120    #[doc = "delay 2 line (CCIR PAL)"]
121    #[inline(always)]
122    pub fn ccir_pal(self) -> &'a mut crate::W<REG> {
123        self.variant(YUV_EAV_SAV_F_LINE_DLY_A::CCIR_PAL)
124    }
125    #[doc = "delay 3 line (CCIR NTSC)"]
126    #[inline(always)]
127    pub fn ccir_ntsc(self) -> &'a mut crate::W<REG> {
128        self.variant(YUV_EAV_SAV_F_LINE_DLY_A::CCIR_NTSC)
129    }
130}
131#[doc = "Field `yuv_sm` reader - Serial YUV mode Output sequence 2-pixel-pair of every scan line."]
132pub type YUV_SM_R = crate::FieldReader<YUV_SM_A>;
133#[doc = "Serial YUV mode Output sequence 2-pixel-pair of every scan line.\n\nValue on reset: 0"]
134#[derive(Clone, Copy, Debug, PartialEq, Eq)]
135#[repr(u8)]
136pub enum YUV_SM_A {
137    #[doc = "0: YUYV"]
138    YUYV = 0,
139    #[doc = "1: YVYU"]
140    YVYU = 1,
141    #[doc = "2: UYVY"]
142    UYVY = 2,
143    #[doc = "3: VYUY"]
144    VYUY = 3,
145}
146impl From<YUV_SM_A> for u8 {
147    #[inline(always)]
148    fn from(variant: YUV_SM_A) -> Self {
149        variant as _
150    }
151}
152impl crate::FieldSpec for YUV_SM_A {
153    type Ux = u8;
154}
155impl YUV_SM_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub const fn variant(&self) -> YUV_SM_A {
159        match self.bits {
160            0 => YUV_SM_A::YUYV,
161            1 => YUV_SM_A::YVYU,
162            2 => YUV_SM_A::UYVY,
163            3 => YUV_SM_A::VYUY,
164            _ => unreachable!(),
165        }
166    }
167    #[doc = "YUYV"]
168    #[inline(always)]
169    pub fn is_yuyv(&self) -> bool {
170        *self == YUV_SM_A::YUYV
171    }
172    #[doc = "YVYU"]
173    #[inline(always)]
174    pub fn is_yvyu(&self) -> bool {
175        *self == YUV_SM_A::YVYU
176    }
177    #[doc = "UYVY"]
178    #[inline(always)]
179    pub fn is_uyvy(&self) -> bool {
180        *self == YUV_SM_A::UYVY
181    }
182    #[doc = "VYUY"]
183    #[inline(always)]
184    pub fn is_vyuy(&self) -> bool {
185        *self == YUV_SM_A::VYUY
186    }
187}
188#[doc = "Field `yuv_sm` writer - Serial YUV mode Output sequence 2-pixel-pair of every scan line."]
189pub type YUV_SM_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, YUV_SM_A>;
190impl<'a, REG> YUV_SM_W<'a, REG>
191where
192    REG: crate::Writable + crate::RegisterSpec,
193    REG::Ux: From<u8>,
194{
195    #[doc = "YUYV"]
196    #[inline(always)]
197    pub fn yuyv(self) -> &'a mut crate::W<REG> {
198        self.variant(YUV_SM_A::YUYV)
199    }
200    #[doc = "YVYU"]
201    #[inline(always)]
202    pub fn yvyu(self) -> &'a mut crate::W<REG> {
203        self.variant(YUV_SM_A::YVYU)
204    }
205    #[doc = "UYVY"]
206    #[inline(always)]
207    pub fn uyvy(self) -> &'a mut crate::W<REG> {
208        self.variant(YUV_SM_A::UYVY)
209    }
210    #[doc = "VYUY"]
211    #[inline(always)]
212    pub fn vyuy(self) -> &'a mut crate::W<REG> {
213        self.variant(YUV_SM_A::VYUY)
214    }
215}
216#[doc = "Field `rgb888_even_order` reader - Serial RGB888 mode Output sequence at even lines of the panel (line 2, 4, 6, 8...)."]
217pub type RGB888_EVEN_ORDER_R = crate::FieldReader<RGB888_EVEN_ORDER_A>;
218#[doc = "Serial RGB888 mode Output sequence at even lines of the panel (line 2, 4, 6, 8...).\n\nValue on reset: 0"]
219#[derive(Clone, Copy, Debug, PartialEq, Eq)]
220#[repr(u8)]
221pub enum RGB888_EVEN_ORDER_A {
222    #[doc = "0: R -> G -> B"]
223    RGB = 0,
224    #[doc = "1: B -> R -> G"]
225    BRG = 1,
226    #[doc = "2: G -> B -> R"]
227    GBR = 2,
228}
229impl From<RGB888_EVEN_ORDER_A> for u8 {
230    #[inline(always)]
231    fn from(variant: RGB888_EVEN_ORDER_A) -> Self {
232        variant as _
233    }
234}
235impl crate::FieldSpec for RGB888_EVEN_ORDER_A {
236    type Ux = u8;
237}
238impl RGB888_EVEN_ORDER_R {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Option<RGB888_EVEN_ORDER_A> {
242        match self.bits {
243            0 => Some(RGB888_EVEN_ORDER_A::RGB),
244            1 => Some(RGB888_EVEN_ORDER_A::BRG),
245            2 => Some(RGB888_EVEN_ORDER_A::GBR),
246            _ => None,
247        }
248    }
249    #[doc = "R -> G -> B"]
250    #[inline(always)]
251    pub fn is_rgb(&self) -> bool {
252        *self == RGB888_EVEN_ORDER_A::RGB
253    }
254    #[doc = "B -> R -> G"]
255    #[inline(always)]
256    pub fn is_brg(&self) -> bool {
257        *self == RGB888_EVEN_ORDER_A::BRG
258    }
259    #[doc = "G -> B -> R"]
260    #[inline(always)]
261    pub fn is_gbr(&self) -> bool {
262        *self == RGB888_EVEN_ORDER_A::GBR
263    }
264}
265#[doc = "Field `rgb888_even_order` writer - Serial RGB888 mode Output sequence at even lines of the panel (line 2, 4, 6, 8...)."]
266pub type RGB888_EVEN_ORDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, RGB888_EVEN_ORDER_A>;
267impl<'a, REG> RGB888_EVEN_ORDER_W<'a, REG>
268where
269    REG: crate::Writable + crate::RegisterSpec,
270    REG::Ux: From<u8>,
271{
272    #[doc = "R -> G -> B"]
273    #[inline(always)]
274    pub fn rgb(self) -> &'a mut crate::W<REG> {
275        self.variant(RGB888_EVEN_ORDER_A::RGB)
276    }
277    #[doc = "B -> R -> G"]
278    #[inline(always)]
279    pub fn brg(self) -> &'a mut crate::W<REG> {
280        self.variant(RGB888_EVEN_ORDER_A::BRG)
281    }
282    #[doc = "G -> B -> R"]
283    #[inline(always)]
284    pub fn gbr(self) -> &'a mut crate::W<REG> {
285        self.variant(RGB888_EVEN_ORDER_A::GBR)
286    }
287}
288#[doc = "Field `rgb888_odd_order` reader - Serial RGB888 mode Output sequence at odd lines of the panel (line 1, 3, 5, 7...)."]
289pub type RGB888_ODD_ORDER_R = crate::FieldReader<RGB888_ODD_ORDER_A>;
290#[doc = "Serial RGB888 mode Output sequence at odd lines of the panel (line 1, 3, 5, 7...).\n\nValue on reset: 0"]
291#[derive(Clone, Copy, Debug, PartialEq, Eq)]
292#[repr(u8)]
293pub enum RGB888_ODD_ORDER_A {
294    #[doc = "0: R -> G -> B"]
295    RGB = 0,
296    #[doc = "1: B -> R -> G"]
297    BRG = 1,
298    #[doc = "2: G -> B -> R"]
299    GBR = 2,
300}
301impl From<RGB888_ODD_ORDER_A> for u8 {
302    #[inline(always)]
303    fn from(variant: RGB888_ODD_ORDER_A) -> Self {
304        variant as _
305    }
306}
307impl crate::FieldSpec for RGB888_ODD_ORDER_A {
308    type Ux = u8;
309}
310impl RGB888_ODD_ORDER_R {
311    #[doc = "Get enumerated values variant"]
312    #[inline(always)]
313    pub const fn variant(&self) -> Option<RGB888_ODD_ORDER_A> {
314        match self.bits {
315            0 => Some(RGB888_ODD_ORDER_A::RGB),
316            1 => Some(RGB888_ODD_ORDER_A::BRG),
317            2 => Some(RGB888_ODD_ORDER_A::GBR),
318            _ => None,
319        }
320    }
321    #[doc = "R -> G -> B"]
322    #[inline(always)]
323    pub fn is_rgb(&self) -> bool {
324        *self == RGB888_ODD_ORDER_A::RGB
325    }
326    #[doc = "B -> R -> G"]
327    #[inline(always)]
328    pub fn is_brg(&self) -> bool {
329        *self == RGB888_ODD_ORDER_A::BRG
330    }
331    #[doc = "G -> B -> R"]
332    #[inline(always)]
333    pub fn is_gbr(&self) -> bool {
334        *self == RGB888_ODD_ORDER_A::GBR
335    }
336}
337#[doc = "Field `rgb888_odd_order` writer - Serial RGB888 mode Output sequence at odd lines of the panel (line 1, 3, 5, 7...)."]
338pub type RGB888_ODD_ORDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, RGB888_ODD_ORDER_A>;
339impl<'a, REG> RGB888_ODD_ORDER_W<'a, REG>
340where
341    REG: crate::Writable + crate::RegisterSpec,
342    REG::Ux: From<u8>,
343{
344    #[doc = "R -> G -> B"]
345    #[inline(always)]
346    pub fn rgb(self) -> &'a mut crate::W<REG> {
347        self.variant(RGB888_ODD_ORDER_A::RGB)
348    }
349    #[doc = "B -> R -> G"]
350    #[inline(always)]
351    pub fn brg(self) -> &'a mut crate::W<REG> {
352        self.variant(RGB888_ODD_ORDER_A::BRG)
353    }
354    #[doc = "G -> B -> R"]
355    #[inline(always)]
356    pub fn gbr(self) -> &'a mut crate::W<REG> {
357        self.variant(RGB888_ODD_ORDER_A::GBR)
358    }
359}
360#[doc = "Field `hv_mode` reader - Set the HV mode of LCD controller"]
361pub type HV_MODE_R = crate::FieldReader<HV_MODE_A>;
362#[doc = "Set the HV mode of LCD controller\n\nValue on reset: 0"]
363#[derive(Clone, Copy, Debug, PartialEq, Eq)]
364#[repr(u8)]
365pub enum HV_MODE_A {
366    #[doc = "0: 24-bit/1-cycle parallel mode"]
367    PARALLEL = 0,
368    #[doc = "8: 8-bit/3-cycle RGB serial mode (RGB888)"]
369    RGB888 = 8,
370    #[doc = "10: 8-bit/4-cycle Dummy RGB (DRGB)"]
371    DRGB = 10,
372    #[doc = "11: 8-bit/4-cycle RGB Dummy (RGBD)"]
373    RGBD = 11,
374    #[doc = "12: 8-bit/2-cycle YUV serial mode (CCIR656)"]
375    CCIR656 = 12,
376}
377impl From<HV_MODE_A> for u8 {
378    #[inline(always)]
379    fn from(variant: HV_MODE_A) -> Self {
380        variant as _
381    }
382}
383impl crate::FieldSpec for HV_MODE_A {
384    type Ux = u8;
385}
386impl HV_MODE_R {
387    #[doc = "Get enumerated values variant"]
388    #[inline(always)]
389    pub const fn variant(&self) -> Option<HV_MODE_A> {
390        match self.bits {
391            0 => Some(HV_MODE_A::PARALLEL),
392            8 => Some(HV_MODE_A::RGB888),
393            10 => Some(HV_MODE_A::DRGB),
394            11 => Some(HV_MODE_A::RGBD),
395            12 => Some(HV_MODE_A::CCIR656),
396            _ => None,
397        }
398    }
399    #[doc = "24-bit/1-cycle parallel mode"]
400    #[inline(always)]
401    pub fn is_parallel(&self) -> bool {
402        *self == HV_MODE_A::PARALLEL
403    }
404    #[doc = "8-bit/3-cycle RGB serial mode (RGB888)"]
405    #[inline(always)]
406    pub fn is_rgb888(&self) -> bool {
407        *self == HV_MODE_A::RGB888
408    }
409    #[doc = "8-bit/4-cycle Dummy RGB (DRGB)"]
410    #[inline(always)]
411    pub fn is_drgb(&self) -> bool {
412        *self == HV_MODE_A::DRGB
413    }
414    #[doc = "8-bit/4-cycle RGB Dummy (RGBD)"]
415    #[inline(always)]
416    pub fn is_rgbd(&self) -> bool {
417        *self == HV_MODE_A::RGBD
418    }
419    #[doc = "8-bit/2-cycle YUV serial mode (CCIR656)"]
420    #[inline(always)]
421    pub fn is_ccir656(&self) -> bool {
422        *self == HV_MODE_A::CCIR656
423    }
424}
425#[doc = "Field `hv_mode` writer - Set the HV mode of LCD controller"]
426pub type HV_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, HV_MODE_A>;
427impl<'a, REG> HV_MODE_W<'a, REG>
428where
429    REG: crate::Writable + crate::RegisterSpec,
430    REG::Ux: From<u8>,
431{
432    #[doc = "24-bit/1-cycle parallel mode"]
433    #[inline(always)]
434    pub fn parallel(self) -> &'a mut crate::W<REG> {
435        self.variant(HV_MODE_A::PARALLEL)
436    }
437    #[doc = "8-bit/3-cycle RGB serial mode (RGB888)"]
438    #[inline(always)]
439    pub fn rgb888(self) -> &'a mut crate::W<REG> {
440        self.variant(HV_MODE_A::RGB888)
441    }
442    #[doc = "8-bit/4-cycle Dummy RGB (DRGB)"]
443    #[inline(always)]
444    pub fn drgb(self) -> &'a mut crate::W<REG> {
445        self.variant(HV_MODE_A::DRGB)
446    }
447    #[doc = "8-bit/4-cycle RGB Dummy (RGBD)"]
448    #[inline(always)]
449    pub fn rgbd(self) -> &'a mut crate::W<REG> {
450        self.variant(HV_MODE_A::RGBD)
451    }
452    #[doc = "8-bit/2-cycle YUV serial mode (CCIR656)"]
453    #[inline(always)]
454    pub fn ccir656(self) -> &'a mut crate::W<REG> {
455        self.variant(HV_MODE_A::CCIR656)
456    }
457}
458impl R {
459    #[doc = "Bit 19 - LCD convert source from RGB to YUV.\n\nOnly valid when HV mode is “1100”."]
460    #[inline(always)]
461    pub fn ccir_csc_dis(&self) -> CCIR_CSC_DIS_R {
462        CCIR_CSC_DIS_R::new(((self.bits >> 19) & 1) != 0)
463    }
464    #[doc = "Bits 20:21 - Set the delay line mode."]
465    #[inline(always)]
466    pub fn yuv_eav_sav_f_line_dly(&self) -> YUV_EAV_SAV_F_LINE_DLY_R {
467        YUV_EAV_SAV_F_LINE_DLY_R::new(((self.bits >> 20) & 3) as u8)
468    }
469    #[doc = "Bits 22:23 - Serial YUV mode Output sequence 2-pixel-pair of every scan line."]
470    #[inline(always)]
471    pub fn yuv_sm(&self) -> YUV_SM_R {
472        YUV_SM_R::new(((self.bits >> 22) & 3) as u8)
473    }
474    #[doc = "Bits 24:25 - Serial RGB888 mode Output sequence at even lines of the panel (line 2, 4, 6, 8...)."]
475    #[inline(always)]
476    pub fn rgb888_even_order(&self) -> RGB888_EVEN_ORDER_R {
477        RGB888_EVEN_ORDER_R::new(((self.bits >> 24) & 3) as u8)
478    }
479    #[doc = "Bits 26:27 - Serial RGB888 mode Output sequence at odd lines of the panel (line 1, 3, 5, 7...)."]
480    #[inline(always)]
481    pub fn rgb888_odd_order(&self) -> RGB888_ODD_ORDER_R {
482        RGB888_ODD_ORDER_R::new(((self.bits >> 26) & 3) as u8)
483    }
484    #[doc = "Bits 28:31 - Set the HV mode of LCD controller"]
485    #[inline(always)]
486    pub fn hv_mode(&self) -> HV_MODE_R {
487        HV_MODE_R::new(((self.bits >> 28) & 0x0f) as u8)
488    }
489}
490impl W {
491    #[doc = "Bit 19 - LCD convert source from RGB to YUV.\n\nOnly valid when HV mode is “1100”."]
492    #[inline(always)]
493    #[must_use]
494    pub fn ccir_csc_dis(&mut self) -> CCIR_CSC_DIS_W<LCD_HV_IF_SPEC> {
495        CCIR_CSC_DIS_W::new(self, 19)
496    }
497    #[doc = "Bits 20:21 - Set the delay line mode."]
498    #[inline(always)]
499    #[must_use]
500    pub fn yuv_eav_sav_f_line_dly(&mut self) -> YUV_EAV_SAV_F_LINE_DLY_W<LCD_HV_IF_SPEC> {
501        YUV_EAV_SAV_F_LINE_DLY_W::new(self, 20)
502    }
503    #[doc = "Bits 22:23 - Serial YUV mode Output sequence 2-pixel-pair of every scan line."]
504    #[inline(always)]
505    #[must_use]
506    pub fn yuv_sm(&mut self) -> YUV_SM_W<LCD_HV_IF_SPEC> {
507        YUV_SM_W::new(self, 22)
508    }
509    #[doc = "Bits 24:25 - Serial RGB888 mode Output sequence at even lines of the panel (line 2, 4, 6, 8...)."]
510    #[inline(always)]
511    #[must_use]
512    pub fn rgb888_even_order(&mut self) -> RGB888_EVEN_ORDER_W<LCD_HV_IF_SPEC> {
513        RGB888_EVEN_ORDER_W::new(self, 24)
514    }
515    #[doc = "Bits 26:27 - Serial RGB888 mode Output sequence at odd lines of the panel (line 1, 3, 5, 7...)."]
516    #[inline(always)]
517    #[must_use]
518    pub fn rgb888_odd_order(&mut self) -> RGB888_ODD_ORDER_W<LCD_HV_IF_SPEC> {
519        RGB888_ODD_ORDER_W::new(self, 26)
520    }
521    #[doc = "Bits 28:31 - Set the HV mode of LCD controller"]
522    #[inline(always)]
523    #[must_use]
524    pub fn hv_mode(&mut self) -> HV_MODE_W<LCD_HV_IF_SPEC> {
525        HV_MODE_W::new(self, 28)
526    }
527    #[doc = r" Writes raw bits to the register."]
528    #[doc = r""]
529    #[doc = r" # Safety"]
530    #[doc = r""]
531    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
532    #[inline(always)]
533    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
534        self.bits = bits;
535        self
536    }
537}
538#[doc = "LCD HV Panel Interface Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_hv_if::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_hv_if::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
539pub struct LCD_HV_IF_SPEC;
540impl crate::RegisterSpec for LCD_HV_IF_SPEC {
541    type Ux = u32;
542}
543#[doc = "`read()` method returns [`lcd_hv_if::R`](R) reader structure"]
544impl crate::Readable for LCD_HV_IF_SPEC {}
545#[doc = "`write(|w| ..)` method takes [`lcd_hv_if::W`](W) writer structure"]
546impl crate::Writable for LCD_HV_IF_SPEC {
547    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
548    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
549}
550#[doc = "`reset()` method sets lcd_hv_if to value 0"]
551impl crate::Resettable for LCD_HV_IF_SPEC {
552    const RESET_VALUE: Self::Ux = 0;
553}
d1_pac/tcon_lcd0/lcd_hv_if.rs

d1_pac/tcon_lcd0/
lcd_hv_if.rs
