d1_pac/tcon_lcd0/
lcd_cpu_tri5.rs

1#[doc = "Register `lcd_cpu_tri5` reader"]
2pub type R = crate::R<LCD_CPU_TRI5_SPEC>;
3#[doc = "Register `lcd_cpu_tri5` writer"]
4pub type W = crate::W<LCD_CPU_TRI5_SPEC>;
5#[doc = "Field `d23_to_d0_non_first_valid` reader - Valid in Block except first."]
6pub type D23_TO_D0_NON_FIRST_VALID_R = crate::FieldReader<u32>;
7#[doc = "Field `d23_to_d0_non_first_valid` writer - Valid in Block except first."]
8pub type D23_TO_D0_NON_FIRST_VALID_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
9#[doc = "Field `a1_non_first_valid` reader - Valid in Block except first."]
10pub type A1_NON_FIRST_VALID_R = crate::BitReader;
11#[doc = "Field `a1_non_first_valid` writer - Valid in Block except first."]
12pub type A1_NON_FIRST_VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 0:23 - Valid in Block except first."]
15    #[inline(always)]
16    pub fn d23_to_d0_non_first_valid(&self) -> D23_TO_D0_NON_FIRST_VALID_R {
17        D23_TO_D0_NON_FIRST_VALID_R::new(self.bits & 0x00ff_ffff)
18    }
19    #[doc = "Bit 24 - Valid in Block except first."]
20    #[inline(always)]
21    pub fn a1_non_first_valid(&self) -> A1_NON_FIRST_VALID_R {
22        A1_NON_FIRST_VALID_R::new(((self.bits >> 24) & 1) != 0)
23    }
24}
25impl W {
26    #[doc = "Bits 0:23 - Valid in Block except first."]
27    #[inline(always)]
28    #[must_use]
29    pub fn d23_to_d0_non_first_valid(&mut self) -> D23_TO_D0_NON_FIRST_VALID_W<LCD_CPU_TRI5_SPEC> {
30        D23_TO_D0_NON_FIRST_VALID_W::new(self, 0)
31    }
32    #[doc = "Bit 24 - Valid in Block except first."]
33    #[inline(always)]
34    #[must_use]
35    pub fn a1_non_first_valid(&mut self) -> A1_NON_FIRST_VALID_W<LCD_CPU_TRI5_SPEC> {
36        A1_NON_FIRST_VALID_W::new(self, 24)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "LCD CPU Panel Trigger Register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_cpu_tri5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_cpu_tri5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct LCD_CPU_TRI5_SPEC;
51impl crate::RegisterSpec for LCD_CPU_TRI5_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`lcd_cpu_tri5::R`](R) reader structure"]
55impl crate::Readable for LCD_CPU_TRI5_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`lcd_cpu_tri5::W`](W) writer structure"]
57impl crate::Writable for LCD_CPU_TRI5_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets lcd_cpu_tri5 to value 0"]
62impl crate::Resettable for LCD_CPU_TRI5_SPEC {
63    const RESET_VALUE: Self::Ux = 0;
64}
d1_pac/tcon_lcd0/lcd_cpu_tri5.rs

d1_pac/tcon_lcd0/
lcd_cpu_tri5.rs
