d1_pac/tcon_lcd0/
lcd_cpu_tri4.rs

1#[doc = "Register `lcd_cpu_tri4` reader"]
2pub type R = crate::R<LCD_CPU_TRI4_SPEC>;
3#[doc = "Register `lcd_cpu_tri4` writer"]
4pub type W = crate::W<LCD_CPU_TRI4_SPEC>;
5#[doc = "Field `d23_to_d0_first_valid` reader - Valid in first Block."]
6pub type D23_TO_D0_FIRST_VALID_R = crate::FieldReader<u32>;
7#[doc = "Field `d23_to_d0_first_valid` writer - Valid in first Block."]
8pub type D23_TO_D0_FIRST_VALID_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
9#[doc = "Field `a1_first_valid` reader - Valid in first Block."]
10pub type A1_FIRST_VALID_R = crate::BitReader;
11#[doc = "Field `a1_first_valid` writer - Valid in first Block."]
12pub type A1_FIRST_VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `plug_mode_en` reader - Enable the plug mode used in dsi command mode."]
14pub type PLUG_MODE_EN_R = crate::BitReader<PLUG_MODE_EN_A>;
15#[doc = "Enable the plug mode used in dsi command mode.\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17pub enum PLUG_MODE_EN_A {
18    #[doc = "0: Disable"]
19    DISABLE = 0,
20    #[doc = "1: Enable"]
21    ENABLE = 1,
22}
23impl From<PLUG_MODE_EN_A> for bool {
24    #[inline(always)]
25    fn from(variant: PLUG_MODE_EN_A) -> Self {
26        variant as u8 != 0
27    }
28}
29impl PLUG_MODE_EN_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> PLUG_MODE_EN_A {
33        match self.bits {
34            false => PLUG_MODE_EN_A::DISABLE,
35            true => PLUG_MODE_EN_A::ENABLE,
36        }
37    }
38    #[doc = "Disable"]
39    #[inline(always)]
40    pub fn is_disable(&self) -> bool {
41        *self == PLUG_MODE_EN_A::DISABLE
42    }
43    #[doc = "Enable"]
44    #[inline(always)]
45    pub fn is_enable(&self) -> bool {
46        *self == PLUG_MODE_EN_A::ENABLE
47    }
48}
49#[doc = "Field `plug_mode_en` writer - Enable the plug mode used in dsi command mode."]
50pub type PLUG_MODE_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLUG_MODE_EN_A>;
51impl<'a, REG> PLUG_MODE_EN_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "Disable"]
56    #[inline(always)]
57    pub fn disable(self) -> &'a mut crate::W<REG> {
58        self.variant(PLUG_MODE_EN_A::DISABLE)
59    }
60    #[doc = "Enable"]
61    #[inline(always)]
62    pub fn enable(self) -> &'a mut crate::W<REG> {
63        self.variant(PLUG_MODE_EN_A::ENABLE)
64    }
65}
66impl R {
67    #[doc = "Bits 0:23 - Valid in first Block."]
68    #[inline(always)]
69    pub fn d23_to_d0_first_valid(&self) -> D23_TO_D0_FIRST_VALID_R {
70        D23_TO_D0_FIRST_VALID_R::new(self.bits & 0x00ff_ffff)
71    }
72    #[doc = "Bit 24 - Valid in first Block."]
73    #[inline(always)]
74    pub fn a1_first_valid(&self) -> A1_FIRST_VALID_R {
75        A1_FIRST_VALID_R::new(((self.bits >> 24) & 1) != 0)
76    }
77    #[doc = "Bit 28 - Enable the plug mode used in dsi command mode."]
78    #[inline(always)]
79    pub fn plug_mode_en(&self) -> PLUG_MODE_EN_R {
80        PLUG_MODE_EN_R::new(((self.bits >> 28) & 1) != 0)
81    }
82}
83impl W {
84    #[doc = "Bits 0:23 - Valid in first Block."]
85    #[inline(always)]
86    #[must_use]
87    pub fn d23_to_d0_first_valid(&mut self) -> D23_TO_D0_FIRST_VALID_W<LCD_CPU_TRI4_SPEC> {
88        D23_TO_D0_FIRST_VALID_W::new(self, 0)
89    }
90    #[doc = "Bit 24 - Valid in first Block."]
91    #[inline(always)]
92    #[must_use]
93    pub fn a1_first_valid(&mut self) -> A1_FIRST_VALID_W<LCD_CPU_TRI4_SPEC> {
94        A1_FIRST_VALID_W::new(self, 24)
95    }
96    #[doc = "Bit 28 - Enable the plug mode used in dsi command mode."]
97    #[inline(always)]
98    #[must_use]
99    pub fn plug_mode_en(&mut self) -> PLUG_MODE_EN_W<LCD_CPU_TRI4_SPEC> {
100        PLUG_MODE_EN_W::new(self, 28)
101    }
102    #[doc = r" Writes raw bits to the register."]
103    #[doc = r""]
104    #[doc = r" # Safety"]
105    #[doc = r""]
106    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
107    #[inline(always)]
108    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
109        self.bits = bits;
110        self
111    }
112}
113#[doc = "LCD CPU Panel Trigger Register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_cpu_tri4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_cpu_tri4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
114pub struct LCD_CPU_TRI4_SPEC;
115impl crate::RegisterSpec for LCD_CPU_TRI4_SPEC {
116    type Ux = u32;
117}
118#[doc = "`read()` method returns [`lcd_cpu_tri4::R`](R) reader structure"]
119impl crate::Readable for LCD_CPU_TRI4_SPEC {}
120#[doc = "`write(|w| ..)` method takes [`lcd_cpu_tri4::W`](W) writer structure"]
121impl crate::Writable for LCD_CPU_TRI4_SPEC {
122    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
123    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
124}
125#[doc = "`reset()` method sets lcd_cpu_tri4 to value 0"]
126impl crate::Resettable for LCD_CPU_TRI4_SPEC {
127    const RESET_VALUE: Self::Ux = 0;
128}
d1_pac/tcon_lcd0/lcd_cpu_tri4.rs

d1_pac/tcon_lcd0/
lcd_cpu_tri4.rs
