d1_pac/tcon_lcd0/
lcd_cpu_tri3.rs

1#[doc = "Register `lcd_cpu_tri3` reader"]
2pub type R = crate::R<LCD_CPU_TRI3_SPEC>;
3#[doc = "Register `lcd_cpu_tri3` writer"]
4pub type W = crate::W<LCD_CPU_TRI3_SPEC>;
5#[doc = "Field `counter_m` reader - The value of counter factor"]
6pub type COUNTER_M_R = crate::FieldReader;
7#[doc = "Field `counter_m` writer - The value of counter factor"]
8pub type COUNTER_M_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `counter_n` reader - The value of counter factor"]
10pub type COUNTER_N_R = crate::FieldReader<u16>;
11#[doc = "Field `counter_n` writer - The value of counter factor"]
12pub type COUNTER_N_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13#[doc = "Field `tri_int_mode` reader - When set as 01, the Tri_Counter_Int occurs in cycle of (Count_N+1) * (Count_M+1) * 4 dclk.\n\nWhen set as 10 or 11, the io0 is map as TE input."]
14pub type TRI_INT_MODE_R = crate::FieldReader<TRI_INT_MODE_A>;
15#[doc = "When set as 01, the Tri_Counter_Int occurs in cycle of (Count_N+1) * (Count_M+1) * 4 dclk.\n\nWhen set as 10 or 11, the io0 is map as TE input.\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17#[repr(u8)]
18pub enum TRI_INT_MODE_A {
19    #[doc = "0: Disable"]
20    DISABLE = 0,
21    #[doc = "1: Counter mode"]
22    C_OUNTER = 1,
23    #[doc = "2: TE rising mode"]
24    TE_RISING = 2,
25    #[doc = "3: TE falling mode"]
26    TE_FALLING = 3,
27}
28impl From<TRI_INT_MODE_A> for u8 {
29    #[inline(always)]
30    fn from(variant: TRI_INT_MODE_A) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for TRI_INT_MODE_A {
35    type Ux = u8;
36}
37impl TRI_INT_MODE_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> TRI_INT_MODE_A {
41        match self.bits {
42            0 => TRI_INT_MODE_A::DISABLE,
43            1 => TRI_INT_MODE_A::C_OUNTER,
44            2 => TRI_INT_MODE_A::TE_RISING,
45            3 => TRI_INT_MODE_A::TE_FALLING,
46            _ => unreachable!(),
47        }
48    }
49    #[doc = "Disable"]
50    #[inline(always)]
51    pub fn is_disable(&self) -> bool {
52        *self == TRI_INT_MODE_A::DISABLE
53    }
54    #[doc = "Counter mode"]
55    #[inline(always)]
56    pub fn is_c_ounter(&self) -> bool {
57        *self == TRI_INT_MODE_A::C_OUNTER
58    }
59    #[doc = "TE rising mode"]
60    #[inline(always)]
61    pub fn is_te_rising(&self) -> bool {
62        *self == TRI_INT_MODE_A::TE_RISING
63    }
64    #[doc = "TE falling mode"]
65    #[inline(always)]
66    pub fn is_te_falling(&self) -> bool {
67        *self == TRI_INT_MODE_A::TE_FALLING
68    }
69}
70#[doc = "Field `tri_int_mode` writer - When set as 01, the Tri_Counter_Int occurs in cycle of (Count_N+1) * (Count_M+1) * 4 dclk.\n\nWhen set as 10 or 11, the io0 is map as TE input."]
71pub type TRI_INT_MODE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, TRI_INT_MODE_A>;
72impl<'a, REG> TRI_INT_MODE_W<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75    REG::Ux: From<u8>,
76{
77    #[doc = "Disable"]
78    #[inline(always)]
79    pub fn disable(self) -> &'a mut crate::W<REG> {
80        self.variant(TRI_INT_MODE_A::DISABLE)
81    }
82    #[doc = "Counter mode"]
83    #[inline(always)]
84    pub fn c_ounter(self) -> &'a mut crate::W<REG> {
85        self.variant(TRI_INT_MODE_A::C_OUNTER)
86    }
87    #[doc = "TE rising mode"]
88    #[inline(always)]
89    pub fn te_rising(self) -> &'a mut crate::W<REG> {
90        self.variant(TRI_INT_MODE_A::TE_RISING)
91    }
92    #[doc = "TE falling mode"]
93    #[inline(always)]
94    pub fn te_falling(self) -> &'a mut crate::W<REG> {
95        self.variant(TRI_INT_MODE_A::TE_FALLING)
96    }
97}
98impl R {
99    #[doc = "Bits 0:7 - The value of counter factor"]
100    #[inline(always)]
101    pub fn counter_m(&self) -> COUNTER_M_R {
102        COUNTER_M_R::new((self.bits & 0xff) as u8)
103    }
104    #[doc = "Bits 8:23 - The value of counter factor"]
105    #[inline(always)]
106    pub fn counter_n(&self) -> COUNTER_N_R {
107        COUNTER_N_R::new(((self.bits >> 8) & 0xffff) as u16)
108    }
109    #[doc = "Bits 28:29 - When set as 01, the Tri_Counter_Int occurs in cycle of (Count_N+1) * (Count_M+1) * 4 dclk.\n\nWhen set as 10 or 11, the io0 is map as TE input."]
110    #[inline(always)]
111    pub fn tri_int_mode(&self) -> TRI_INT_MODE_R {
112        TRI_INT_MODE_R::new(((self.bits >> 28) & 3) as u8)
113    }
114}
115impl W {
116    #[doc = "Bits 0:7 - The value of counter factor"]
117    #[inline(always)]
118    #[must_use]
119    pub fn counter_m(&mut self) -> COUNTER_M_W<LCD_CPU_TRI3_SPEC> {
120        COUNTER_M_W::new(self, 0)
121    }
122    #[doc = "Bits 8:23 - The value of counter factor"]
123    #[inline(always)]
124    #[must_use]
125    pub fn counter_n(&mut self) -> COUNTER_N_W<LCD_CPU_TRI3_SPEC> {
126        COUNTER_N_W::new(self, 8)
127    }
128    #[doc = "Bits 28:29 - When set as 01, the Tri_Counter_Int occurs in cycle of (Count_N+1) * (Count_M+1) * 4 dclk.\n\nWhen set as 10 or 11, the io0 is map as TE input."]
129    #[inline(always)]
130    #[must_use]
131    pub fn tri_int_mode(&mut self) -> TRI_INT_MODE_W<LCD_CPU_TRI3_SPEC> {
132        TRI_INT_MODE_W::new(self, 28)
133    }
134    #[doc = r" Writes raw bits to the register."]
135    #[doc = r""]
136    #[doc = r" # Safety"]
137    #[doc = r""]
138    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
139    #[inline(always)]
140    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
141        self.bits = bits;
142        self
143    }
144}
145#[doc = "LCD CPU Panel Trigger Register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_cpu_tri3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_cpu_tri3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
146pub struct LCD_CPU_TRI3_SPEC;
147impl crate::RegisterSpec for LCD_CPU_TRI3_SPEC {
148    type Ux = u32;
149}
150#[doc = "`read()` method returns [`lcd_cpu_tri3::R`](R) reader structure"]
151impl crate::Readable for LCD_CPU_TRI3_SPEC {}
152#[doc = "`write(|w| ..)` method takes [`lcd_cpu_tri3::W`](W) writer structure"]
153impl crate::Writable for LCD_CPU_TRI3_SPEC {
154    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
155    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
156}
157#[doc = "`reset()` method sets lcd_cpu_tri3 to value 0"]
158impl crate::Resettable for LCD_CPU_TRI3_SPEC {
159    const RESET_VALUE: Self::Ux = 0;
160}
d1_pac/tcon_lcd0/lcd_cpu_tri3.rs

d1_pac/tcon_lcd0/
lcd_cpu_tri3.rs
