d1_pac/tcon_lcd0/
lcd_cpu_tri2.rs

1#[doc = "Register `lcd_cpu_tri2` reader"]
2pub type R = crate::R<LCD_CPU_TRI2_SPEC>;
3#[doc = "Register `lcd_cpu_tri2` writer"]
4pub type W = crate::W<LCD_CPU_TRI2_SPEC>;
5#[doc = "Field `trans_start_set` reader - Usual set as the length of a line."]
6pub type TRANS_START_SET_R = crate::FieldReader<u16>;
7#[doc = "Field `trans_start_set` writer - Usual set as the length of a line."]
8pub type TRANS_START_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
9#[doc = "Field `sync_mode` reader - Set the sync mode in CPU interface."]
10pub type SYNC_MODE_R = crate::FieldReader;
11#[doc = "Field `sync_mode` writer - Set the sync mode in CPU interface."]
12pub type SYNC_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `trans_start_mode` reader - Select the FIFOs used in CPU mode."]
14pub type TRANS_START_MODE_R = crate::BitReader<TRANS_START_MODE_A>;
15#[doc = "Select the FIFOs used in CPU mode.\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17pub enum TRANS_START_MODE_A {
18    #[doc = "0: ECC_FIFO+TRI_FIFO"]
19    ECC_FIFO_TRI_FIFO = 0,
20    #[doc = "1: TRI_FIFO"]
21    TRI_FIFO = 1,
22}
23impl From<TRANS_START_MODE_A> for bool {
24    #[inline(always)]
25    fn from(variant: TRANS_START_MODE_A) -> Self {
26        variant as u8 != 0
27    }
28}
29impl TRANS_START_MODE_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> TRANS_START_MODE_A {
33        match self.bits {
34            false => TRANS_START_MODE_A::ECC_FIFO_TRI_FIFO,
35            true => TRANS_START_MODE_A::TRI_FIFO,
36        }
37    }
38    #[doc = "ECC_FIFO+TRI_FIFO"]
39    #[inline(always)]
40    pub fn is_ecc_fifo_tri_fifo(&self) -> bool {
41        *self == TRANS_START_MODE_A::ECC_FIFO_TRI_FIFO
42    }
43    #[doc = "TRI_FIFO"]
44    #[inline(always)]
45    pub fn is_tri_fifo(&self) -> bool {
46        *self == TRANS_START_MODE_A::TRI_FIFO
47    }
48}
49#[doc = "Field `trans_start_mode` writer - Select the FIFOs used in CPU mode."]
50pub type TRANS_START_MODE_W<'a, REG> = crate::BitWriter<'a, REG, TRANS_START_MODE_A>;
51impl<'a, REG> TRANS_START_MODE_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "ECC_FIFO+TRI_FIFO"]
56    #[inline(always)]
57    pub fn ecc_fifo_tri_fifo(self) -> &'a mut crate::W<REG> {
58        self.variant(TRANS_START_MODE_A::ECC_FIFO_TRI_FIFO)
59    }
60    #[doc = "TRI_FIFO"]
61    #[inline(always)]
62    pub fn tri_fifo(self) -> &'a mut crate::W<REG> {
63        self.variant(TRANS_START_MODE_A::TRI_FIFO)
64    }
65}
66#[doc = "Field `start_dly` reader - T_dly = (Start_Delay +1) * be_clk*8."]
67pub type START_DLY_R = crate::FieldReader<u16>;
68#[doc = "Field `start_dly` writer - T_dly = (Start_Delay +1) * be_clk*8."]
69pub type START_DLY_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
70impl R {
71    #[doc = "Bits 0:12 - Usual set as the length of a line."]
72    #[inline(always)]
73    pub fn trans_start_set(&self) -> TRANS_START_SET_R {
74        TRANS_START_SET_R::new((self.bits & 0x1fff) as u16)
75    }
76    #[doc = "Bits 13:14 - Set the sync mode in CPU interface."]
77    #[inline(always)]
78    pub fn sync_mode(&self) -> SYNC_MODE_R {
79        SYNC_MODE_R::new(((self.bits >> 13) & 3) as u8)
80    }
81    #[doc = "Bit 15 - Select the FIFOs used in CPU mode."]
82    #[inline(always)]
83    pub fn trans_start_mode(&self) -> TRANS_START_MODE_R {
84        TRANS_START_MODE_R::new(((self.bits >> 15) & 1) != 0)
85    }
86    #[doc = "Bits 16:31 - T_dly = (Start_Delay +1) * be_clk*8."]
87    #[inline(always)]
88    pub fn start_dly(&self) -> START_DLY_R {
89        START_DLY_R::new(((self.bits >> 16) & 0xffff) as u16)
90    }
91}
92impl W {
93    #[doc = "Bits 0:12 - Usual set as the length of a line."]
94    #[inline(always)]
95    #[must_use]
96    pub fn trans_start_set(&mut self) -> TRANS_START_SET_W<LCD_CPU_TRI2_SPEC> {
97        TRANS_START_SET_W::new(self, 0)
98    }
99    #[doc = "Bits 13:14 - Set the sync mode in CPU interface."]
100    #[inline(always)]
101    #[must_use]
102    pub fn sync_mode(&mut self) -> SYNC_MODE_W<LCD_CPU_TRI2_SPEC> {
103        SYNC_MODE_W::new(self, 13)
104    }
105    #[doc = "Bit 15 - Select the FIFOs used in CPU mode."]
106    #[inline(always)]
107    #[must_use]
108    pub fn trans_start_mode(&mut self) -> TRANS_START_MODE_W<LCD_CPU_TRI2_SPEC> {
109        TRANS_START_MODE_W::new(self, 15)
110    }
111    #[doc = "Bits 16:31 - T_dly = (Start_Delay +1) * be_clk*8."]
112    #[inline(always)]
113    #[must_use]
114    pub fn start_dly(&mut self) -> START_DLY_W<LCD_CPU_TRI2_SPEC> {
115        START_DLY_W::new(self, 16)
116    }
117    #[doc = r" Writes raw bits to the register."]
118    #[doc = r""]
119    #[doc = r" # Safety"]
120    #[doc = r""]
121    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
122    #[inline(always)]
123    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
124        self.bits = bits;
125        self
126    }
127}
128#[doc = "LCD CPU Panel Trigger Register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_cpu_tri2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_cpu_tri2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
129pub struct LCD_CPU_TRI2_SPEC;
130impl crate::RegisterSpec for LCD_CPU_TRI2_SPEC {
131    type Ux = u32;
132}
133#[doc = "`read()` method returns [`lcd_cpu_tri2::R`](R) reader structure"]
134impl crate::Readable for LCD_CPU_TRI2_SPEC {}
135#[doc = "`write(|w| ..)` method takes [`lcd_cpu_tri2::W`](W) writer structure"]
136impl crate::Writable for LCD_CPU_TRI2_SPEC {
137    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
138    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
139}
140#[doc = "`reset()` method sets lcd_cpu_tri2 to value 0"]
141impl crate::Resettable for LCD_CPU_TRI2_SPEC {
142    const RESET_VALUE: Self::Ux = 0;
143}
d1_pac/tcon_lcd0/lcd_cpu_tri2.rs

d1_pac/tcon_lcd0/
lcd_cpu_tri2.rs
