d1_pac/tcon_lcd0/
lcd_cpu_if.rs

1#[doc = "Register `lcd_cpu_if` reader"]
2pub type R = crate::R<LCD_CPU_IF_SPEC>;
3#[doc = "Register `lcd_cpu_if` writer"]
4pub type W = crate::W<LCD_CPU_IF_SPEC>;
5#[doc = "Field `tri_en` reader - Enable trigger mode"]
6pub type TRI_EN_R = crate::BitReader<TRI_EN_A>;
7#[doc = "Enable trigger mode\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TRI_EN_A {
10    #[doc = "0: Trigger mode disable"]
11    DISABLE = 0,
12    #[doc = "1: Trigger mode enable"]
13    ENABLE = 1,
14}
15impl From<TRI_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: TRI_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TRI_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TRI_EN_A {
25        match self.bits {
26            false => TRI_EN_A::DISABLE,
27            true => TRI_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Trigger mode disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == TRI_EN_A::DISABLE
34    }
35    #[doc = "Trigger mode enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == TRI_EN_A::ENABLE
39    }
40}
41#[doc = "Field `tri_en` writer - Enable trigger mode"]
42pub type TRI_EN_W<'a, REG> = crate::BitWriter<'a, REG, TRI_EN_A>;
43impl<'a, REG> TRI_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Trigger mode disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(TRI_EN_A::DISABLE)
51    }
52    #[doc = "Trigger mode enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(TRI_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `tri_start` reader - Software must make sure that write '1' only when this flag is '0'.\n\nWriting '1' starts a frame flush and writing '0' has no effect.\n\nThis flag indicates the frame flush is running."]
59pub type TRI_START_R = crate::BitReader;
60#[doc = "Field `tri_start` writer - Software must make sure that write '1' only when this flag is '0'.\n\nWriting '1' starts a frame flush and writing '0' has no effect.\n\nThis flag indicates the frame flush is running."]
61pub type TRI_START_W<'a, REG> = crate::BitWriter1S<'a, REG>;
62#[doc = "Field `tri_fifo_en` reader - Enable the trigger FIFO"]
63pub type TRI_FIFO_EN_R = crate::BitReader<TRI_FIFO_EN_A>;
64#[doc = "Enable the trigger FIFO\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum TRI_FIFO_EN_A {
67    #[doc = "0: Disable"]
68    DISABLE = 0,
69    #[doc = "1: Enable"]
70    ENABLE = 1,
71}
72impl From<TRI_FIFO_EN_A> for bool {
73    #[inline(always)]
74    fn from(variant: TRI_FIFO_EN_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl TRI_FIFO_EN_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> TRI_FIFO_EN_A {
82        match self.bits {
83            false => TRI_FIFO_EN_A::DISABLE,
84            true => TRI_FIFO_EN_A::ENABLE,
85        }
86    }
87    #[doc = "Disable"]
88    #[inline(always)]
89    pub fn is_disable(&self) -> bool {
90        *self == TRI_FIFO_EN_A::DISABLE
91    }
92    #[doc = "Enable"]
93    #[inline(always)]
94    pub fn is_enable(&self) -> bool {
95        *self == TRI_FIFO_EN_A::ENABLE
96    }
97}
98#[doc = "Field `tri_fifo_en` writer - Enable the trigger FIFO"]
99pub type TRI_FIFO_EN_W<'a, REG> = crate::BitWriter<'a, REG, TRI_FIFO_EN_A>;
100impl<'a, REG> TRI_FIFO_EN_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "Disable"]
105    #[inline(always)]
106    pub fn disable(self) -> &'a mut crate::W<REG> {
107        self.variant(TRI_FIFO_EN_A::DISABLE)
108    }
109    #[doc = "Enable"]
110    #[inline(always)]
111    pub fn enable(self) -> &'a mut crate::W<REG> {
112        self.variant(TRI_FIFO_EN_A::ENABLE)
113    }
114}
115#[doc = "Field `tri_fifo_bist_en` reader - Entry address is 0xFF8"]
116pub type TRI_FIFO_BIST_EN_R = crate::BitReader<TRI_FIFO_BIST_EN_A>;
117#[doc = "Entry address is 0xFF8\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119pub enum TRI_FIFO_BIST_EN_A {
120    #[doc = "0: Disable"]
121    DISABLE = 0,
122    #[doc = "1: Enable"]
123    ENABLE = 1,
124}
125impl From<TRI_FIFO_BIST_EN_A> for bool {
126    #[inline(always)]
127    fn from(variant: TRI_FIFO_BIST_EN_A) -> Self {
128        variant as u8 != 0
129    }
130}
131impl TRI_FIFO_BIST_EN_R {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub const fn variant(&self) -> TRI_FIFO_BIST_EN_A {
135        match self.bits {
136            false => TRI_FIFO_BIST_EN_A::DISABLE,
137            true => TRI_FIFO_BIST_EN_A::ENABLE,
138        }
139    }
140    #[doc = "Disable"]
141    #[inline(always)]
142    pub fn is_disable(&self) -> bool {
143        *self == TRI_FIFO_BIST_EN_A::DISABLE
144    }
145    #[doc = "Enable"]
146    #[inline(always)]
147    pub fn is_enable(&self) -> bool {
148        *self == TRI_FIFO_BIST_EN_A::ENABLE
149    }
150}
151#[doc = "Field `tri_fifo_bist_en` writer - Entry address is 0xFF8"]
152pub type TRI_FIFO_BIST_EN_W<'a, REG> = crate::BitWriter<'a, REG, TRI_FIFO_BIST_EN_A>;
153impl<'a, REG> TRI_FIFO_BIST_EN_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156{
157    #[doc = "Disable"]
158    #[inline(always)]
159    pub fn disable(self) -> &'a mut crate::W<REG> {
160        self.variant(TRI_FIFO_BIST_EN_A::DISABLE)
161    }
162    #[doc = "Enable"]
163    #[inline(always)]
164    pub fn enable(self) -> &'a mut crate::W<REG> {
165        self.variant(TRI_FIFO_BIST_EN_A::ENABLE)
166    }
167}
168#[doc = "Field `flush` reader - Direct transfer mode\n\nIf it is enabled, FIFO1 is regardless of the HV timing, the pixels data keep being transferred unless the input FIFO was empty.\n\nData output rate is controlled by DCLK."]
169pub type FLUSH_R = crate::BitReader;
170#[doc = "Field `flush` writer - Direct transfer mode\n\nIf it is enabled, FIFO1 is regardless of the HV timing, the pixels data keep being transferred unless the input FIFO was empty.\n\nData output rate is controlled by DCLK."]
171pub type FLUSH_W<'a, REG> = crate::BitWriter<'a, REG>;
172#[doc = "Field `auto` reader - Auto transfer mode\n\nIf it is 1, all the valid data during this frame are written to panel.\n\nNote: This bit is sampled by Vsync."]
173pub type AUTO_R = crate::BitReader;
174#[doc = "Field `auto` writer - Auto transfer mode\n\nIf it is 1, all the valid data during this frame are written to panel.\n\nNote: This bit is sampled by Vsync."]
175pub type AUTO_W<'a, REG> = crate::BitWriter<'a, REG>;
176#[doc = "Field `rd_flag` reader - The status of read operation."]
177pub type RD_FLAG_R = crate::BitReader<RD_FLAG_A>;
178#[doc = "The status of read operation.\n\nValue on reset: 0"]
179#[derive(Clone, Copy, Debug, PartialEq, Eq)]
180pub enum RD_FLAG_A {
181    #[doc = "0: Read operation is finishing"]
182    FINISHING = 0,
183    #[doc = "1: Read operation is pending"]
184    PENDING = 1,
185}
186impl From<RD_FLAG_A> for bool {
187    #[inline(always)]
188    fn from(variant: RD_FLAG_A) -> Self {
189        variant as u8 != 0
190    }
191}
192impl RD_FLAG_R {
193    #[doc = "Get enumerated values variant"]
194    #[inline(always)]
195    pub const fn variant(&self) -> RD_FLAG_A {
196        match self.bits {
197            false => RD_FLAG_A::FINISHING,
198            true => RD_FLAG_A::PENDING,
199        }
200    }
201    #[doc = "Read operation is finishing"]
202    #[inline(always)]
203    pub fn is_finishing(&self) -> bool {
204        *self == RD_FLAG_A::FINISHING
205    }
206    #[doc = "Read operation is pending"]
207    #[inline(always)]
208    pub fn is_pending(&self) -> bool {
209        *self == RD_FLAG_A::PENDING
210    }
211}
212#[doc = "Field `wr_flag` reader - The status of write operation."]
213pub type WR_FLAG_R = crate::BitReader<WR_FLAG_A>;
214#[doc = "The status of write operation.\n\nValue on reset: 0"]
215#[derive(Clone, Copy, Debug, PartialEq, Eq)]
216pub enum WR_FLAG_A {
217    #[doc = "0: Write operation is finishing"]
218    FINISHING = 0,
219    #[doc = "1: Write operation is pending"]
220    PENDING = 1,
221}
222impl From<WR_FLAG_A> for bool {
223    #[inline(always)]
224    fn from(variant: WR_FLAG_A) -> Self {
225        variant as u8 != 0
226    }
227}
228impl WR_FLAG_R {
229    #[doc = "Get enumerated values variant"]
230    #[inline(always)]
231    pub const fn variant(&self) -> WR_FLAG_A {
232        match self.bits {
233            false => WR_FLAG_A::FINISHING,
234            true => WR_FLAG_A::PENDING,
235        }
236    }
237    #[doc = "Write operation is finishing"]
238    #[inline(always)]
239    pub fn is_finishing(&self) -> bool {
240        *self == WR_FLAG_A::FINISHING
241    }
242    #[doc = "Write operation is pending"]
243    #[inline(always)]
244    pub fn is_pending(&self) -> bool {
245        *self == WR_FLAG_A::PENDING
246    }
247}
248#[doc = "Field `ca` reader - Pin A1 value in 8080 mode WR/RD execute"]
249pub type CA_R = crate::BitReader;
250#[doc = "Field `ca` writer - Pin A1 value in 8080 mode WR/RD execute"]
251pub type CA_W<'a, REG> = crate::BitWriter<'a, REG>;
252#[doc = "Field `da` reader - Pin A1 value in 8080 mode auto/flash states"]
253pub type DA_R = crate::BitReader;
254#[doc = "Field `da` writer - Pin A1 value in 8080 mode auto/flash states"]
255pub type DA_W<'a, REG> = crate::BitWriter<'a, REG>;
256#[doc = "Field `cpu_mode` reader - Set the cpu interface work mode"]
257pub type CPU_MODE_R = crate::FieldReader<CPU_MODE_A>;
258#[doc = "Set the cpu interface work mode\n\nValue on reset: 0"]
259#[derive(Clone, Copy, Debug, PartialEq, Eq)]
260#[repr(u8)]
261pub enum CPU_MODE_A {
262    #[doc = "0: 18-bit/256K mode"]
263    B_IT18_256K_MODE = 0,
264    #[doc = "2: 16-bit mode0"]
265    B_IT16_MODE0 = 2,
266    #[doc = "4: 16-bit mode1"]
267    B_IT16_MODE1 = 4,
268    #[doc = "6: 16-bit mode2"]
269    B_IT16_MODE2 = 6,
270    #[doc = "8: 16-bit mode3"]
271    B_IT16_MODE3 = 8,
272    #[doc = "10: 9-bit mode"]
273    B_IT9_MODE = 10,
274    #[doc = "12: 8-bit 256K mode"]
275    B_IT8_256K_MODE = 12,
276    #[doc = "14: 8-bit 65K mode"]
277    B_IT8_65K_MODE = 14,
278    #[doc = "1: 24-bit for DSI"]
279    B_IT24_FOR_DSI = 1,
280}
281impl From<CPU_MODE_A> for u8 {
282    #[inline(always)]
283    fn from(variant: CPU_MODE_A) -> Self {
284        variant as _
285    }
286}
287impl crate::FieldSpec for CPU_MODE_A {
288    type Ux = u8;
289}
290impl CPU_MODE_R {
291    #[doc = "Get enumerated values variant"]
292    #[inline(always)]
293    pub const fn variant(&self) -> Option<CPU_MODE_A> {
294        match self.bits {
295            0 => Some(CPU_MODE_A::B_IT18_256K_MODE),
296            2 => Some(CPU_MODE_A::B_IT16_MODE0),
297            4 => Some(CPU_MODE_A::B_IT16_MODE1),
298            6 => Some(CPU_MODE_A::B_IT16_MODE2),
299            8 => Some(CPU_MODE_A::B_IT16_MODE3),
300            10 => Some(CPU_MODE_A::B_IT9_MODE),
301            12 => Some(CPU_MODE_A::B_IT8_256K_MODE),
302            14 => Some(CPU_MODE_A::B_IT8_65K_MODE),
303            1 => Some(CPU_MODE_A::B_IT24_FOR_DSI),
304            _ => None,
305        }
306    }
307    #[doc = "18-bit/256K mode"]
308    #[inline(always)]
309    pub fn is_b_it18_256k_mode(&self) -> bool {
310        *self == CPU_MODE_A::B_IT18_256K_MODE
311    }
312    #[doc = "16-bit mode0"]
313    #[inline(always)]
314    pub fn is_b_it16_mode0(&self) -> bool {
315        *self == CPU_MODE_A::B_IT16_MODE0
316    }
317    #[doc = "16-bit mode1"]
318    #[inline(always)]
319    pub fn is_b_it16_mode1(&self) -> bool {
320        *self == CPU_MODE_A::B_IT16_MODE1
321    }
322    #[doc = "16-bit mode2"]
323    #[inline(always)]
324    pub fn is_b_it16_mode2(&self) -> bool {
325        *self == CPU_MODE_A::B_IT16_MODE2
326    }
327    #[doc = "16-bit mode3"]
328    #[inline(always)]
329    pub fn is_b_it16_mode3(&self) -> bool {
330        *self == CPU_MODE_A::B_IT16_MODE3
331    }
332    #[doc = "9-bit mode"]
333    #[inline(always)]
334    pub fn is_b_it9_mode(&self) -> bool {
335        *self == CPU_MODE_A::B_IT9_MODE
336    }
337    #[doc = "8-bit 256K mode"]
338    #[inline(always)]
339    pub fn is_b_it8_256k_mode(&self) -> bool {
340        *self == CPU_MODE_A::B_IT8_256K_MODE
341    }
342    #[doc = "8-bit 65K mode"]
343    #[inline(always)]
344    pub fn is_b_it8_65k_mode(&self) -> bool {
345        *self == CPU_MODE_A::B_IT8_65K_MODE
346    }
347    #[doc = "24-bit for DSI"]
348    #[inline(always)]
349    pub fn is_b_it24_for_dsi(&self) -> bool {
350        *self == CPU_MODE_A::B_IT24_FOR_DSI
351    }
352}
353#[doc = "Field `cpu_mode` writer - Set the cpu interface work mode"]
354pub type CPU_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, CPU_MODE_A>;
355impl<'a, REG> CPU_MODE_W<'a, REG>
356where
357    REG: crate::Writable + crate::RegisterSpec,
358    REG::Ux: From<u8>,
359{
360    #[doc = "18-bit/256K mode"]
361    #[inline(always)]
362    pub fn b_it18_256k_mode(self) -> &'a mut crate::W<REG> {
363        self.variant(CPU_MODE_A::B_IT18_256K_MODE)
364    }
365    #[doc = "16-bit mode0"]
366    #[inline(always)]
367    pub fn b_it16_mode0(self) -> &'a mut crate::W<REG> {
368        self.variant(CPU_MODE_A::B_IT16_MODE0)
369    }
370    #[doc = "16-bit mode1"]
371    #[inline(always)]
372    pub fn b_it16_mode1(self) -> &'a mut crate::W<REG> {
373        self.variant(CPU_MODE_A::B_IT16_MODE1)
374    }
375    #[doc = "16-bit mode2"]
376    #[inline(always)]
377    pub fn b_it16_mode2(self) -> &'a mut crate::W<REG> {
378        self.variant(CPU_MODE_A::B_IT16_MODE2)
379    }
380    #[doc = "16-bit mode3"]
381    #[inline(always)]
382    pub fn b_it16_mode3(self) -> &'a mut crate::W<REG> {
383        self.variant(CPU_MODE_A::B_IT16_MODE3)
384    }
385    #[doc = "9-bit mode"]
386    #[inline(always)]
387    pub fn b_it9_mode(self) -> &'a mut crate::W<REG> {
388        self.variant(CPU_MODE_A::B_IT9_MODE)
389    }
390    #[doc = "8-bit 256K mode"]
391    #[inline(always)]
392    pub fn b_it8_256k_mode(self) -> &'a mut crate::W<REG> {
393        self.variant(CPU_MODE_A::B_IT8_256K_MODE)
394    }
395    #[doc = "8-bit 65K mode"]
396    #[inline(always)]
397    pub fn b_it8_65k_mode(self) -> &'a mut crate::W<REG> {
398        self.variant(CPU_MODE_A::B_IT8_65K_MODE)
399    }
400    #[doc = "24-bit for DSI"]
401    #[inline(always)]
402    pub fn b_it24_for_dsi(self) -> &'a mut crate::W<REG> {
403        self.variant(CPU_MODE_A::B_IT24_FOR_DSI)
404    }
405}
406impl R {
407    #[doc = "Bit 0 - Enable trigger mode"]
408    #[inline(always)]
409    pub fn tri_en(&self) -> TRI_EN_R {
410        TRI_EN_R::new((self.bits & 1) != 0)
411    }
412    #[doc = "Bit 1 - Software must make sure that write '1' only when this flag is '0'.\n\nWriting '1' starts a frame flush and writing '0' has no effect.\n\nThis flag indicates the frame flush is running."]
413    #[inline(always)]
414    pub fn tri_start(&self) -> TRI_START_R {
415        TRI_START_R::new(((self.bits >> 1) & 1) != 0)
416    }
417    #[doc = "Bit 2 - Enable the trigger FIFO"]
418    #[inline(always)]
419    pub fn tri_fifo_en(&self) -> TRI_FIFO_EN_R {
420        TRI_FIFO_EN_R::new(((self.bits >> 2) & 1) != 0)
421    }
422    #[doc = "Bit 3 - Entry address is 0xFF8"]
423    #[inline(always)]
424    pub fn tri_fifo_bist_en(&self) -> TRI_FIFO_BIST_EN_R {
425        TRI_FIFO_BIST_EN_R::new(((self.bits >> 3) & 1) != 0)
426    }
427    #[doc = "Bit 16 - Direct transfer mode\n\nIf it is enabled, FIFO1 is regardless of the HV timing, the pixels data keep being transferred unless the input FIFO was empty.\n\nData output rate is controlled by DCLK."]
428    #[inline(always)]
429    pub fn flush(&self) -> FLUSH_R {
430        FLUSH_R::new(((self.bits >> 16) & 1) != 0)
431    }
432    #[doc = "Bit 17 - Auto transfer mode\n\nIf it is 1, all the valid data during this frame are written to panel.\n\nNote: This bit is sampled by Vsync."]
433    #[inline(always)]
434    pub fn auto(&self) -> AUTO_R {
435        AUTO_R::new(((self.bits >> 17) & 1) != 0)
436    }
437    #[doc = "Bit 22 - The status of read operation."]
438    #[inline(always)]
439    pub fn rd_flag(&self) -> RD_FLAG_R {
440        RD_FLAG_R::new(((self.bits >> 22) & 1) != 0)
441    }
442    #[doc = "Bit 23 - The status of write operation."]
443    #[inline(always)]
444    pub fn wr_flag(&self) -> WR_FLAG_R {
445        WR_FLAG_R::new(((self.bits >> 23) & 1) != 0)
446    }
447    #[doc = "Bit 25 - Pin A1 value in 8080 mode WR/RD execute"]
448    #[inline(always)]
449    pub fn ca(&self) -> CA_R {
450        CA_R::new(((self.bits >> 25) & 1) != 0)
451    }
452    #[doc = "Bit 26 - Pin A1 value in 8080 mode auto/flash states"]
453    #[inline(always)]
454    pub fn da(&self) -> DA_R {
455        DA_R::new(((self.bits >> 26) & 1) != 0)
456    }
457    #[doc = "Bits 28:31 - Set the cpu interface work mode"]
458    #[inline(always)]
459    pub fn cpu_mode(&self) -> CPU_MODE_R {
460        CPU_MODE_R::new(((self.bits >> 28) & 0x0f) as u8)
461    }
462}
463impl W {
464    #[doc = "Bit 0 - Enable trigger mode"]
465    #[inline(always)]
466    #[must_use]
467    pub fn tri_en(&mut self) -> TRI_EN_W<LCD_CPU_IF_SPEC> {
468        TRI_EN_W::new(self, 0)
469    }
470    #[doc = "Bit 1 - Software must make sure that write '1' only when this flag is '0'.\n\nWriting '1' starts a frame flush and writing '0' has no effect.\n\nThis flag indicates the frame flush is running."]
471    #[inline(always)]
472    #[must_use]
473    pub fn tri_start(&mut self) -> TRI_START_W<LCD_CPU_IF_SPEC> {
474        TRI_START_W::new(self, 1)
475    }
476    #[doc = "Bit 2 - Enable the trigger FIFO"]
477    #[inline(always)]
478    #[must_use]
479    pub fn tri_fifo_en(&mut self) -> TRI_FIFO_EN_W<LCD_CPU_IF_SPEC> {
480        TRI_FIFO_EN_W::new(self, 2)
481    }
482    #[doc = "Bit 3 - Entry address is 0xFF8"]
483    #[inline(always)]
484    #[must_use]
485    pub fn tri_fifo_bist_en(&mut self) -> TRI_FIFO_BIST_EN_W<LCD_CPU_IF_SPEC> {
486        TRI_FIFO_BIST_EN_W::new(self, 3)
487    }
488    #[doc = "Bit 16 - Direct transfer mode\n\nIf it is enabled, FIFO1 is regardless of the HV timing, the pixels data keep being transferred unless the input FIFO was empty.\n\nData output rate is controlled by DCLK."]
489    #[inline(always)]
490    #[must_use]
491    pub fn flush(&mut self) -> FLUSH_W<LCD_CPU_IF_SPEC> {
492        FLUSH_W::new(self, 16)
493    }
494    #[doc = "Bit 17 - Auto transfer mode\n\nIf it is 1, all the valid data during this frame are written to panel.\n\nNote: This bit is sampled by Vsync."]
495    #[inline(always)]
496    #[must_use]
497    pub fn auto(&mut self) -> AUTO_W<LCD_CPU_IF_SPEC> {
498        AUTO_W::new(self, 17)
499    }
500    #[doc = "Bit 25 - Pin A1 value in 8080 mode WR/RD execute"]
501    #[inline(always)]
502    #[must_use]
503    pub fn ca(&mut self) -> CA_W<LCD_CPU_IF_SPEC> {
504        CA_W::new(self, 25)
505    }
506    #[doc = "Bit 26 - Pin A1 value in 8080 mode auto/flash states"]
507    #[inline(always)]
508    #[must_use]
509    pub fn da(&mut self) -> DA_W<LCD_CPU_IF_SPEC> {
510        DA_W::new(self, 26)
511    }
512    #[doc = "Bits 28:31 - Set the cpu interface work mode"]
513    #[inline(always)]
514    #[must_use]
515    pub fn cpu_mode(&mut self) -> CPU_MODE_W<LCD_CPU_IF_SPEC> {
516        CPU_MODE_W::new(self, 28)
517    }
518    #[doc = r" Writes raw bits to the register."]
519    #[doc = r""]
520    #[doc = r" # Safety"]
521    #[doc = r""]
522    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
523    #[inline(always)]
524    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
525        self.bits = bits;
526        self
527    }
528}
529#[doc = "LCD CPU Panel Interface Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_cpu_if::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_cpu_if::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
530pub struct LCD_CPU_IF_SPEC;
531impl crate::RegisterSpec for LCD_CPU_IF_SPEC {
532    type Ux = u32;
533}
534#[doc = "`read()` method returns [`lcd_cpu_if::R`](R) reader structure"]
535impl crate::Readable for LCD_CPU_IF_SPEC {}
536#[doc = "`write(|w| ..)` method takes [`lcd_cpu_if::W`](W) writer structure"]
537impl crate::Writable for LCD_CPU_IF_SPEC {
538    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
539    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x02;
540}
541#[doc = "`reset()` method sets lcd_cpu_if to value 0"]
542impl crate::Resettable for LCD_CPU_IF_SPEC {
543    const RESET_VALUE: Self::Ux = 0;
544}
d1_pac/tcon_lcd0/lcd_cpu_if.rs

d1_pac/tcon_lcd0/
lcd_cpu_if.rs
