d1_pac/tcon_lcd0/
fsync_gen_dly.rs

1#[doc = "Register `fsync_gen_dly` reader"]
2pub type R = crate::R<FSYNC_GEN_DLY_SPEC>;
3#[doc = "Register `fsync_gen_dly` writer"]
4pub type W = crate::W<FSYNC_GEN_DLY_SPEC>;
5#[doc = "Field `sensor_act1_time` reader - Delay 0-4095 Pixel clk Period\n\nThe actual delay is sensor_act1_time+1."]
6pub type SENSOR_ACT1_TIME_R = crate::FieldReader<u16>;
7#[doc = "Field `sensor_act1_time` writer - Delay 0-4095 Pixel clk Period\n\nThe actual delay is sensor_act1_time+1."]
8pub type SENSOR_ACT1_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Field `sensor_act0_time` reader - Delay 0-4095 Pixel clk Period\n\nThe actual delay is sensor_act0_time+1."]
10pub type SENSOR_ACT0_TIME_R = crate::FieldReader<u16>;
11#[doc = "Field `sensor_act0_time` writer - Delay 0-4095 Pixel clk Period\n\nThe actual delay is sensor_act0_time+1."]
12pub type SENSOR_ACT0_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
13impl R {
14    #[doc = "Bits 0:11 - Delay 0-4095 Pixel clk Period\n\nThe actual delay is sensor_act1_time+1."]
15    #[inline(always)]
16    pub fn sensor_act1_time(&self) -> SENSOR_ACT1_TIME_R {
17        SENSOR_ACT1_TIME_R::new((self.bits & 0x0fff) as u16)
18    }
19    #[doc = "Bits 16:27 - Delay 0-4095 Pixel clk Period\n\nThe actual delay is sensor_act0_time+1."]
20    #[inline(always)]
21    pub fn sensor_act0_time(&self) -> SENSOR_ACT0_TIME_R {
22        SENSOR_ACT0_TIME_R::new(((self.bits >> 16) & 0x0fff) as u16)
23    }
24}
25impl W {
26    #[doc = "Bits 0:11 - Delay 0-4095 Pixel clk Period\n\nThe actual delay is sensor_act1_time+1."]
27    #[inline(always)]
28    #[must_use]
29    pub fn sensor_act1_time(&mut self) -> SENSOR_ACT1_TIME_W<FSYNC_GEN_DLY_SPEC> {
30        SENSOR_ACT1_TIME_W::new(self, 0)
31    }
32    #[doc = "Bits 16:27 - Delay 0-4095 Pixel clk Period\n\nThe actual delay is sensor_act0_time+1."]
33    #[inline(always)]
34    #[must_use]
35    pub fn sensor_act0_time(&mut self) -> SENSOR_ACT0_TIME_W<FSYNC_GEN_DLY_SPEC> {
36        SENSOR_ACT0_TIME_W::new(self, 16)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "FSYNC_GEN_DLY\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsync_gen_dly::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsync_gen_dly::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct FSYNC_GEN_DLY_SPEC;
51impl crate::RegisterSpec for FSYNC_GEN_DLY_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`fsync_gen_dly::R`](R) reader structure"]
55impl crate::Readable for FSYNC_GEN_DLY_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`fsync_gen_dly::W`](W) writer structure"]
57impl crate::Writable for FSYNC_GEN_DLY_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets fsync_gen_dly to value 0"]
62impl crate::Resettable for FSYNC_GEN_DLY_SPEC {
63    const RESET_VALUE: Self::Ux = 0;
64}
d1_pac/tcon_lcd0/fsync_gen_dly.rs

d1_pac/tcon_lcd0/
fsync_gen_dly.rs
