d1_pac/tcon_lcd0/
fsync_gen_ctrl.rs

1#[doc = "Register `fsync_gen_ctrl` reader"]
2pub type R = crate::R<FSYNC_GEN_CTRL_SPEC>;
3#[doc = "Register `fsync_gen_ctrl` writer"]
4pub type W = crate::W<FSYNC_GEN_CTRL_SPEC>;
5#[doc = "Field `fsync_gen_en` reader - Fsync Generate Enable"]
6pub type FSYNC_GEN_EN_R = crate::BitReader<FSYNC_GEN_EN_A>;
7#[doc = "Fsync Generate Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum FSYNC_GEN_EN_A {
10    #[doc = "0: Disable"]
11    DISABLE = 0,
12    #[doc = "1: Enable"]
13    ENABLE = 1,
14}
15impl From<FSYNC_GEN_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: FSYNC_GEN_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl FSYNC_GEN_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> FSYNC_GEN_EN_A {
25        match self.bits {
26            false => FSYNC_GEN_EN_A::DISABLE,
27            true => FSYNC_GEN_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == FSYNC_GEN_EN_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == FSYNC_GEN_EN_A::ENABLE
39    }
40}
41#[doc = "Field `fsync_gen_en` writer - Fsync Generate Enable"]
42pub type FSYNC_GEN_EN_W<'a, REG> = crate::BitWriter<'a, REG, FSYNC_GEN_EN_A>;
43impl<'a, REG> FSYNC_GEN_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(FSYNC_GEN_EN_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(FSYNC_GEN_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `sel_vsync_en` reader - Select Vsync Enable"]
59pub type SEL_VSYNC_EN_R = crate::BitReader<SEL_VSYNC_EN_A>;
60#[doc = "Select Vsync Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum SEL_VSYNC_EN_A {
63    #[doc = "0: Select vsync falling edge to start state machine"]
64    FALLING = 0,
65    #[doc = "1: Select vsync rising edge to start state machine"]
66    RISING = 1,
67}
68impl From<SEL_VSYNC_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: SEL_VSYNC_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl SEL_VSYNC_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> SEL_VSYNC_EN_A {
78        match self.bits {
79            false => SEL_VSYNC_EN_A::FALLING,
80            true => SEL_VSYNC_EN_A::RISING,
81        }
82    }
83    #[doc = "Select vsync falling edge to start state machine"]
84    #[inline(always)]
85    pub fn is_falling(&self) -> bool {
86        *self == SEL_VSYNC_EN_A::FALLING
87    }
88    #[doc = "Select vsync rising edge to start state machine"]
89    #[inline(always)]
90    pub fn is_rising(&self) -> bool {
91        *self == SEL_VSYNC_EN_A::RISING
92    }
93}
94#[doc = "Field `sel_vsync_en` writer - Select Vsync Enable"]
95pub type SEL_VSYNC_EN_W<'a, REG> = crate::BitWriter<'a, REG, SEL_VSYNC_EN_A>;
96impl<'a, REG> SEL_VSYNC_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Select vsync falling edge to start state machine"]
101    #[inline(always)]
102    pub fn falling(self) -> &'a mut crate::W<REG> {
103        self.variant(SEL_VSYNC_EN_A::FALLING)
104    }
105    #[doc = "Select vsync rising edge to start state machine"]
106    #[inline(always)]
107    pub fn rising(self) -> &'a mut crate::W<REG> {
108        self.variant(SEL_VSYNC_EN_A::RISING)
109    }
110}
111#[doc = "Field `hsync_pol_sel` reader - Hsync Polarity Select"]
112pub type HSYNC_POL_SEL_R = crate::BitReader<HSYNC_POL_SEL_A>;
113#[doc = "Hsync Polarity Select\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum HSYNC_POL_SEL_A {
116    #[doc = "0: Normal"]
117    NORMAL = 0,
118    #[doc = "1: Opposite hsync to hysnc counter"]
119    O_PPOSITE = 1,
120}
121impl From<HSYNC_POL_SEL_A> for bool {
122    #[inline(always)]
123    fn from(variant: HSYNC_POL_SEL_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl HSYNC_POL_SEL_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> HSYNC_POL_SEL_A {
131        match self.bits {
132            false => HSYNC_POL_SEL_A::NORMAL,
133            true => HSYNC_POL_SEL_A::O_PPOSITE,
134        }
135    }
136    #[doc = "Normal"]
137    #[inline(always)]
138    pub fn is_normal(&self) -> bool {
139        *self == HSYNC_POL_SEL_A::NORMAL
140    }
141    #[doc = "Opposite hsync to hysnc counter"]
142    #[inline(always)]
143    pub fn is_o_pposite(&self) -> bool {
144        *self == HSYNC_POL_SEL_A::O_PPOSITE
145    }
146}
147#[doc = "Field `hsync_pol_sel` writer - Hsync Polarity Select"]
148pub type HSYNC_POL_SEL_W<'a, REG> = crate::BitWriter<'a, REG, HSYNC_POL_SEL_A>;
149impl<'a, REG> HSYNC_POL_SEL_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Normal"]
154    #[inline(always)]
155    pub fn normal(self) -> &'a mut crate::W<REG> {
156        self.variant(HSYNC_POL_SEL_A::NORMAL)
157    }
158    #[doc = "Opposite hsync to hysnc counter"]
159    #[inline(always)]
160    pub fn o_pposite(self) -> &'a mut crate::W<REG> {
161        self.variant(HSYNC_POL_SEL_A::O_PPOSITE)
162    }
163}
164#[doc = "Field `sensor_dis_value` reader - Sensor Disable Value"]
165pub type SENSOR_DIS_VALUE_R = crate::BitReader<SENSOR_DIS_VALUE_A>;
166#[doc = "Sensor Disable Value\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum SENSOR_DIS_VALUE_A {
169    #[doc = "0: Fsync disable period output 0"]
170    OUTPUT_0 = 0,
171    #[doc = "1: Fsync disable period output 1"]
172    OUTPUT_1 = 1,
173}
174impl From<SENSOR_DIS_VALUE_A> for bool {
175    #[inline(always)]
176    fn from(variant: SENSOR_DIS_VALUE_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl SENSOR_DIS_VALUE_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> SENSOR_DIS_VALUE_A {
184        match self.bits {
185            false => SENSOR_DIS_VALUE_A::OUTPUT_0,
186            true => SENSOR_DIS_VALUE_A::OUTPUT_1,
187        }
188    }
189    #[doc = "Fsync disable period output 0"]
190    #[inline(always)]
191    pub fn is_output_0(&self) -> bool {
192        *self == SENSOR_DIS_VALUE_A::OUTPUT_0
193    }
194    #[doc = "Fsync disable period output 1"]
195    #[inline(always)]
196    pub fn is_output_1(&self) -> bool {
197        *self == SENSOR_DIS_VALUE_A::OUTPUT_1
198    }
199}
200#[doc = "Field `sensor_dis_value` writer - Sensor Disable Value"]
201pub type SENSOR_DIS_VALUE_W<'a, REG> = crate::BitWriter<'a, REG, SENSOR_DIS_VALUE_A>;
202impl<'a, REG> SENSOR_DIS_VALUE_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Fsync disable period output 0"]
207    #[inline(always)]
208    pub fn output_0(self) -> &'a mut crate::W<REG> {
209        self.variant(SENSOR_DIS_VALUE_A::OUTPUT_0)
210    }
211    #[doc = "Fsync disable period output 1"]
212    #[inline(always)]
213    pub fn output_1(self) -> &'a mut crate::W<REG> {
214        self.variant(SENSOR_DIS_VALUE_A::OUTPUT_1)
215    }
216}
217#[doc = "Field `sensor_act0_value` reader - Sensor Active0 Value"]
218pub type SENSOR_ACT0_VALUE_R = crate::BitReader<SENSOR_ACT0_VALUE_A>;
219#[doc = "Sensor Active0 Value\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum SENSOR_ACT0_VALUE_A {
222    #[doc = "0: Fsync active_0 period output 0"]
223    OUTPUT_0 = 0,
224    #[doc = "1: Fsync active_0 period output 1"]
225    OUTPUT_1 = 1,
226}
227impl From<SENSOR_ACT0_VALUE_A> for bool {
228    #[inline(always)]
229    fn from(variant: SENSOR_ACT0_VALUE_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl SENSOR_ACT0_VALUE_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> SENSOR_ACT0_VALUE_A {
237        match self.bits {
238            false => SENSOR_ACT0_VALUE_A::OUTPUT_0,
239            true => SENSOR_ACT0_VALUE_A::OUTPUT_1,
240        }
241    }
242    #[doc = "Fsync active_0 period output 0"]
243    #[inline(always)]
244    pub fn is_output_0(&self) -> bool {
245        *self == SENSOR_ACT0_VALUE_A::OUTPUT_0
246    }
247    #[doc = "Fsync active_0 period output 1"]
248    #[inline(always)]
249    pub fn is_output_1(&self) -> bool {
250        *self == SENSOR_ACT0_VALUE_A::OUTPUT_1
251    }
252}
253#[doc = "Field `sensor_act0_value` writer - Sensor Active0 Value"]
254pub type SENSOR_ACT0_VALUE_W<'a, REG> = crate::BitWriter<'a, REG, SENSOR_ACT0_VALUE_A>;
255impl<'a, REG> SENSOR_ACT0_VALUE_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "Fsync active_0 period output 0"]
260    #[inline(always)]
261    pub fn output_0(self) -> &'a mut crate::W<REG> {
262        self.variant(SENSOR_ACT0_VALUE_A::OUTPUT_0)
263    }
264    #[doc = "Fsync active_0 period output 1"]
265    #[inline(always)]
266    pub fn output_1(self) -> &'a mut crate::W<REG> {
267        self.variant(SENSOR_ACT0_VALUE_A::OUTPUT_1)
268    }
269}
270#[doc = "Field `sensor_act1_value` reader - Sensor Active1 Value"]
271pub type SENSOR_ACT1_VALUE_R = crate::BitReader<SENSOR_ACT1_VALUE_A>;
272#[doc = "Sensor Active1 Value\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum SENSOR_ACT1_VALUE_A {
275    #[doc = "0: Fsync active_1 period output 0"]
276    OUTPUT_0 = 0,
277    #[doc = "1: Fsync active_1 period output 1"]
278    OUTPUT_1 = 1,
279}
280impl From<SENSOR_ACT1_VALUE_A> for bool {
281    #[inline(always)]
282    fn from(variant: SENSOR_ACT1_VALUE_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl SENSOR_ACT1_VALUE_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> SENSOR_ACT1_VALUE_A {
290        match self.bits {
291            false => SENSOR_ACT1_VALUE_A::OUTPUT_0,
292            true => SENSOR_ACT1_VALUE_A::OUTPUT_1,
293        }
294    }
295    #[doc = "Fsync active_1 period output 0"]
296    #[inline(always)]
297    pub fn is_output_0(&self) -> bool {
298        *self == SENSOR_ACT1_VALUE_A::OUTPUT_0
299    }
300    #[doc = "Fsync active_1 period output 1"]
301    #[inline(always)]
302    pub fn is_output_1(&self) -> bool {
303        *self == SENSOR_ACT1_VALUE_A::OUTPUT_1
304    }
305}
306#[doc = "Field `sensor_act1_value` writer - Sensor Active1 Value"]
307pub type SENSOR_ACT1_VALUE_W<'a, REG> = crate::BitWriter<'a, REG, SENSOR_ACT1_VALUE_A>;
308impl<'a, REG> SENSOR_ACT1_VALUE_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "Fsync active_1 period output 0"]
313    #[inline(always)]
314    pub fn output_0(self) -> &'a mut crate::W<REG> {
315        self.variant(SENSOR_ACT1_VALUE_A::OUTPUT_0)
316    }
317    #[doc = "Fsync active_1 period output 1"]
318    #[inline(always)]
319    pub fn output_1(self) -> &'a mut crate::W<REG> {
320        self.variant(SENSOR_ACT1_VALUE_A::OUTPUT_1)
321    }
322}
323#[doc = "Field `sensor_dis_time` reader - Delay 0-2047 Hsync Period\n\nWhen hsync_pol_sel is 0, the actual delay is sensor_dis_time-1.\n\nWhen hsync_pol_sel is 1, the actual delay is sensor_dis_time."]
324pub type SENSOR_DIS_TIME_R = crate::FieldReader<u16>;
325#[doc = "Field `sensor_dis_time` writer - Delay 0-2047 Hsync Period\n\nWhen hsync_pol_sel is 0, the actual delay is sensor_dis_time-1.\n\nWhen hsync_pol_sel is 1, the actual delay is sensor_dis_time."]
326pub type SENSOR_DIS_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
327impl R {
328    #[doc = "Bit 0 - Fsync Generate Enable"]
329    #[inline(always)]
330    pub fn fsync_gen_en(&self) -> FSYNC_GEN_EN_R {
331        FSYNC_GEN_EN_R::new((self.bits & 1) != 0)
332    }
333    #[doc = "Bit 1 - Select Vsync Enable"]
334    #[inline(always)]
335    pub fn sel_vsync_en(&self) -> SEL_VSYNC_EN_R {
336        SEL_VSYNC_EN_R::new(((self.bits >> 1) & 1) != 0)
337    }
338    #[doc = "Bit 2 - Hsync Polarity Select"]
339    #[inline(always)]
340    pub fn hsync_pol_sel(&self) -> HSYNC_POL_SEL_R {
341        HSYNC_POL_SEL_R::new(((self.bits >> 2) & 1) != 0)
342    }
343    #[doc = "Bit 4 - Sensor Disable Value"]
344    #[inline(always)]
345    pub fn sensor_dis_value(&self) -> SENSOR_DIS_VALUE_R {
346        SENSOR_DIS_VALUE_R::new(((self.bits >> 4) & 1) != 0)
347    }
348    #[doc = "Bit 5 - Sensor Active0 Value"]
349    #[inline(always)]
350    pub fn sensor_act0_value(&self) -> SENSOR_ACT0_VALUE_R {
351        SENSOR_ACT0_VALUE_R::new(((self.bits >> 5) & 1) != 0)
352    }
353    #[doc = "Bit 6 - Sensor Active1 Value"]
354    #[inline(always)]
355    pub fn sensor_act1_value(&self) -> SENSOR_ACT1_VALUE_R {
356        SENSOR_ACT1_VALUE_R::new(((self.bits >> 6) & 1) != 0)
357    }
358    #[doc = "Bits 8:18 - Delay 0-2047 Hsync Period\n\nWhen hsync_pol_sel is 0, the actual delay is sensor_dis_time-1.\n\nWhen hsync_pol_sel is 1, the actual delay is sensor_dis_time."]
359    #[inline(always)]
360    pub fn sensor_dis_time(&self) -> SENSOR_DIS_TIME_R {
361        SENSOR_DIS_TIME_R::new(((self.bits >> 8) & 0x07ff) as u16)
362    }
363}
364impl W {
365    #[doc = "Bit 0 - Fsync Generate Enable"]
366    #[inline(always)]
367    #[must_use]
368    pub fn fsync_gen_en(&mut self) -> FSYNC_GEN_EN_W<FSYNC_GEN_CTRL_SPEC> {
369        FSYNC_GEN_EN_W::new(self, 0)
370    }
371    #[doc = "Bit 1 - Select Vsync Enable"]
372    #[inline(always)]
373    #[must_use]
374    pub fn sel_vsync_en(&mut self) -> SEL_VSYNC_EN_W<FSYNC_GEN_CTRL_SPEC> {
375        SEL_VSYNC_EN_W::new(self, 1)
376    }
377    #[doc = "Bit 2 - Hsync Polarity Select"]
378    #[inline(always)]
379    #[must_use]
380    pub fn hsync_pol_sel(&mut self) -> HSYNC_POL_SEL_W<FSYNC_GEN_CTRL_SPEC> {
381        HSYNC_POL_SEL_W::new(self, 2)
382    }
383    #[doc = "Bit 4 - Sensor Disable Value"]
384    #[inline(always)]
385    #[must_use]
386    pub fn sensor_dis_value(&mut self) -> SENSOR_DIS_VALUE_W<FSYNC_GEN_CTRL_SPEC> {
387        SENSOR_DIS_VALUE_W::new(self, 4)
388    }
389    #[doc = "Bit 5 - Sensor Active0 Value"]
390    #[inline(always)]
391    #[must_use]
392    pub fn sensor_act0_value(&mut self) -> SENSOR_ACT0_VALUE_W<FSYNC_GEN_CTRL_SPEC> {
393        SENSOR_ACT0_VALUE_W::new(self, 5)
394    }
395    #[doc = "Bit 6 - Sensor Active1 Value"]
396    #[inline(always)]
397    #[must_use]
398    pub fn sensor_act1_value(&mut self) -> SENSOR_ACT1_VALUE_W<FSYNC_GEN_CTRL_SPEC> {
399        SENSOR_ACT1_VALUE_W::new(self, 6)
400    }
401    #[doc = "Bits 8:18 - Delay 0-2047 Hsync Period\n\nWhen hsync_pol_sel is 0, the actual delay is sensor_dis_time-1.\n\nWhen hsync_pol_sel is 1, the actual delay is sensor_dis_time."]
402    #[inline(always)]
403    #[must_use]
404    pub fn sensor_dis_time(&mut self) -> SENSOR_DIS_TIME_W<FSYNC_GEN_CTRL_SPEC> {
405        SENSOR_DIS_TIME_W::new(self, 8)
406    }
407    #[doc = r" Writes raw bits to the register."]
408    #[doc = r""]
409    #[doc = r" # Safety"]
410    #[doc = r""]
411    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
412    #[inline(always)]
413    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
414        self.bits = bits;
415        self
416    }
417}
418#[doc = "FSYNC_GEN_CTRL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsync_gen_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsync_gen_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
419pub struct FSYNC_GEN_CTRL_SPEC;
420impl crate::RegisterSpec for FSYNC_GEN_CTRL_SPEC {
421    type Ux = u32;
422}
423#[doc = "`read()` method returns [`fsync_gen_ctrl::R`](R) reader structure"]
424impl crate::Readable for FSYNC_GEN_CTRL_SPEC {}
425#[doc = "`write(|w| ..)` method takes [`fsync_gen_ctrl::W`](W) writer structure"]
426impl crate::Writable for FSYNC_GEN_CTRL_SPEC {
427    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
428    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
429}
430#[doc = "`reset()` method sets fsync_gen_ctrl to value 0"]
431impl crate::Resettable for FSYNC_GEN_CTRL_SPEC {
432    const RESET_VALUE: Self::Ux = 0;
433}
d1_pac/tcon_lcd0/fsync_gen_ctrl.rs

d1_pac/tcon_lcd0/
fsync_gen_ctrl.rs
