d1_pac/spi_dbi/
spi_isr.rs

1#[doc = "Register `spi_isr` reader"]
2pub type R = crate::R<SPI_ISR_SPEC>;
3#[doc = "Register `spi_isr` writer"]
4pub type W = crate::W<SPI_ISR_SPEC>;
5#[doc = "Field `rf_rdy` reader - RXFIFO Ready"]
6pub type RF_RDY_R = crate::BitReader;
7#[doc = "Field `rf_rdy` writer - RXFIFO Ready"]
8pub type RF_RDY_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `rf_emp` reader - RXFIFO Empty"]
10pub type RF_EMP_R = crate::BitReader<RF_EMP_A>;
11#[doc = "RXFIFO Empty\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum RF_EMP_A {
14    #[doc = "0: `0`"]
15    NOT_EMPTY = 0,
16    #[doc = "1: `1`"]
17    EMPTY = 1,
18}
19impl From<RF_EMP_A> for bool {
20    #[inline(always)]
21    fn from(variant: RF_EMP_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl RF_EMP_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> RF_EMP_A {
29        match self.bits {
30            false => RF_EMP_A::NOT_EMPTY,
31            true => RF_EMP_A::EMPTY,
32        }
33    }
34    #[doc = "`0`"]
35    #[inline(always)]
36    pub fn is_not_empty(&self) -> bool {
37        *self == RF_EMP_A::NOT_EMPTY
38    }
39    #[doc = "`1`"]
40    #[inline(always)]
41    pub fn is_empty(&self) -> bool {
42        *self == RF_EMP_A::EMPTY
43    }
44}
45#[doc = "Field `rf_emp` writer - RXFIFO Empty"]
46pub type RF_EMP_W<'a, REG> = crate::BitWriter<'a, REG, RF_EMP_A>;
47impl<'a, REG> RF_EMP_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn not_empty(self) -> &'a mut crate::W<REG> {
54        self.variant(RF_EMP_A::NOT_EMPTY)
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn empty(self) -> &'a mut crate::W<REG> {
59        self.variant(RF_EMP_A::EMPTY)
60    }
61}
62#[doc = "Field `rf_full` reader - RXFIFO Full"]
63pub type RF_FULL_R = crate::BitReader<RF_FULL_A>;
64#[doc = "RXFIFO Full\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum RF_FULL_A {
67    #[doc = "0: `0`"]
68    NOT_FULL = 0,
69    #[doc = "1: `1`"]
70    FULL = 1,
71}
72impl From<RF_FULL_A> for bool {
73    #[inline(always)]
74    fn from(variant: RF_FULL_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl RF_FULL_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> RF_FULL_A {
82        match self.bits {
83            false => RF_FULL_A::NOT_FULL,
84            true => RF_FULL_A::FULL,
85        }
86    }
87    #[doc = "`0`"]
88    #[inline(always)]
89    pub fn is_not_full(&self) -> bool {
90        *self == RF_FULL_A::NOT_FULL
91    }
92    #[doc = "`1`"]
93    #[inline(always)]
94    pub fn is_full(&self) -> bool {
95        *self == RF_FULL_A::FULL
96    }
97}
98#[doc = "Field `rf_full` writer - RXFIFO Full"]
99pub type RF_FULL_W<'a, REG> = crate::BitWriter<'a, REG, RF_FULL_A>;
100impl<'a, REG> RF_FULL_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "`0`"]
105    #[inline(always)]
106    pub fn not_full(self) -> &'a mut crate::W<REG> {
107        self.variant(RF_FULL_A::NOT_FULL)
108    }
109    #[doc = "`1`"]
110    #[inline(always)]
111    pub fn full(self) -> &'a mut crate::W<REG> {
112        self.variant(RF_FULL_A::FULL)
113    }
114}
115#[doc = "Field `tf_ready` reader - TXFIFO Ready"]
116pub type TF_READY_R = crate::BitReader;
117#[doc = "Field `tf_ready` writer - TXFIFO Ready"]
118pub type TF_READY_W<'a, REG> = crate::BitWriter<'a, REG>;
119#[doc = "Field `tf_emp` reader - TXFIFO Empty"]
120pub type TF_EMP_R = crate::BitReader<TF_EMP_A>;
121#[doc = "TXFIFO Empty\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq, Eq)]
123pub enum TF_EMP_A {
124    #[doc = "0: `0`"]
125    NOT_EMPTY = 0,
126    #[doc = "1: `1`"]
127    EMPTY = 1,
128}
129impl From<TF_EMP_A> for bool {
130    #[inline(always)]
131    fn from(variant: TF_EMP_A) -> Self {
132        variant as u8 != 0
133    }
134}
135impl TF_EMP_R {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub const fn variant(&self) -> TF_EMP_A {
139        match self.bits {
140            false => TF_EMP_A::NOT_EMPTY,
141            true => TF_EMP_A::EMPTY,
142        }
143    }
144    #[doc = "`0`"]
145    #[inline(always)]
146    pub fn is_not_empty(&self) -> bool {
147        *self == TF_EMP_A::NOT_EMPTY
148    }
149    #[doc = "`1`"]
150    #[inline(always)]
151    pub fn is_empty(&self) -> bool {
152        *self == TF_EMP_A::EMPTY
153    }
154}
155#[doc = "Field `tf_emp` writer - TXFIFO Empty"]
156pub type TF_EMP_W<'a, REG> = crate::BitWriter<'a, REG, TF_EMP_A>;
157impl<'a, REG> TF_EMP_W<'a, REG>
158where
159    REG: crate::Writable + crate::RegisterSpec,
160{
161    #[doc = "`0`"]
162    #[inline(always)]
163    pub fn not_empty(self) -> &'a mut crate::W<REG> {
164        self.variant(TF_EMP_A::NOT_EMPTY)
165    }
166    #[doc = "`1`"]
167    #[inline(always)]
168    pub fn empty(self) -> &'a mut crate::W<REG> {
169        self.variant(TF_EMP_A::EMPTY)
170    }
171}
172#[doc = "Field `tf_full` reader - TXFIFO Full"]
173pub type TF_FULL_R = crate::BitReader<TF_FULL_A>;
174#[doc = "TXFIFO Full\n\nValue on reset: 0"]
175#[derive(Clone, Copy, Debug, PartialEq, Eq)]
176pub enum TF_FULL_A {
177    #[doc = "0: `0`"]
178    NOT_FULL = 0,
179    #[doc = "1: `1`"]
180    FULL = 1,
181}
182impl From<TF_FULL_A> for bool {
183    #[inline(always)]
184    fn from(variant: TF_FULL_A) -> Self {
185        variant as u8 != 0
186    }
187}
188impl TF_FULL_R {
189    #[doc = "Get enumerated values variant"]
190    #[inline(always)]
191    pub const fn variant(&self) -> TF_FULL_A {
192        match self.bits {
193            false => TF_FULL_A::NOT_FULL,
194            true => TF_FULL_A::FULL,
195        }
196    }
197    #[doc = "`0`"]
198    #[inline(always)]
199    pub fn is_not_full(&self) -> bool {
200        *self == TF_FULL_A::NOT_FULL
201    }
202    #[doc = "`1`"]
203    #[inline(always)]
204    pub fn is_full(&self) -> bool {
205        *self == TF_FULL_A::FULL
206    }
207}
208#[doc = "Field `tf_full` writer - TXFIFO Full"]
209pub type TF_FULL_W<'a, REG> = crate::BitWriter<'a, REG, TF_FULL_A>;
210impl<'a, REG> TF_FULL_W<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213{
214    #[doc = "`0`"]
215    #[inline(always)]
216    pub fn not_full(self) -> &'a mut crate::W<REG> {
217        self.variant(TF_FULL_A::NOT_FULL)
218    }
219    #[doc = "`1`"]
220    #[inline(always)]
221    pub fn full(self) -> &'a mut crate::W<REG> {
222        self.variant(TF_FULL_A::FULL)
223    }
224}
225#[doc = "Field `rf_ovf` reader - RXFIFO Overflow"]
226pub type RF_OVF_R = crate::BitReader<RF_OVF_A>;
227#[doc = "RXFIFO Overflow\n\nValue on reset: 0"]
228#[derive(Clone, Copy, Debug, PartialEq, Eq)]
229pub enum RF_OVF_A {
230    #[doc = "0: `0`"]
231    NOT_OVERFLOW = 0,
232    #[doc = "1: `1`"]
233    OVERFLOW = 1,
234}
235impl From<RF_OVF_A> for bool {
236    #[inline(always)]
237    fn from(variant: RF_OVF_A) -> Self {
238        variant as u8 != 0
239    }
240}
241impl RF_OVF_R {
242    #[doc = "Get enumerated values variant"]
243    #[inline(always)]
244    pub const fn variant(&self) -> RF_OVF_A {
245        match self.bits {
246            false => RF_OVF_A::NOT_OVERFLOW,
247            true => RF_OVF_A::OVERFLOW,
248        }
249    }
250    #[doc = "`0`"]
251    #[inline(always)]
252    pub fn is_not_overflow(&self) -> bool {
253        *self == RF_OVF_A::NOT_OVERFLOW
254    }
255    #[doc = "`1`"]
256    #[inline(always)]
257    pub fn is_overflow(&self) -> bool {
258        *self == RF_OVF_A::OVERFLOW
259    }
260}
261#[doc = "Field `rf_ovf` writer - RXFIFO Overflow"]
262pub type RF_OVF_W<'a, REG> = crate::BitWriter<'a, REG, RF_OVF_A>;
263impl<'a, REG> RF_OVF_W<'a, REG>
264where
265    REG: crate::Writable + crate::RegisterSpec,
266{
267    #[doc = "`0`"]
268    #[inline(always)]
269    pub fn not_overflow(self) -> &'a mut crate::W<REG> {
270        self.variant(RF_OVF_A::NOT_OVERFLOW)
271    }
272    #[doc = "`1`"]
273    #[inline(always)]
274    pub fn overflow(self) -> &'a mut crate::W<REG> {
275        self.variant(RF_OVF_A::OVERFLOW)
276    }
277}
278#[doc = "Field `rf_udr` reader - RXFIFO Underrun"]
279pub type RF_UDR_R = crate::BitReader<RF_UDR_A>;
280#[doc = "RXFIFO Underrun\n\nValue on reset: 0"]
281#[derive(Clone, Copy, Debug, PartialEq, Eq)]
282pub enum RF_UDR_A {
283    #[doc = "0: `0`"]
284    NOT_UNDERRUN = 0,
285    #[doc = "1: `1`"]
286    UNDERRUN = 1,
287}
288impl From<RF_UDR_A> for bool {
289    #[inline(always)]
290    fn from(variant: RF_UDR_A) -> Self {
291        variant as u8 != 0
292    }
293}
294impl RF_UDR_R {
295    #[doc = "Get enumerated values variant"]
296    #[inline(always)]
297    pub const fn variant(&self) -> RF_UDR_A {
298        match self.bits {
299            false => RF_UDR_A::NOT_UNDERRUN,
300            true => RF_UDR_A::UNDERRUN,
301        }
302    }
303    #[doc = "`0`"]
304    #[inline(always)]
305    pub fn is_not_underrun(&self) -> bool {
306        *self == RF_UDR_A::NOT_UNDERRUN
307    }
308    #[doc = "`1`"]
309    #[inline(always)]
310    pub fn is_underrun(&self) -> bool {
311        *self == RF_UDR_A::UNDERRUN
312    }
313}
314#[doc = "Field `rf_udr` writer - RXFIFO Underrun"]
315pub type RF_UDR_W<'a, REG> = crate::BitWriter<'a, REG, RF_UDR_A>;
316impl<'a, REG> RF_UDR_W<'a, REG>
317where
318    REG: crate::Writable + crate::RegisterSpec,
319{
320    #[doc = "`0`"]
321    #[inline(always)]
322    pub fn not_underrun(self) -> &'a mut crate::W<REG> {
323        self.variant(RF_UDR_A::NOT_UNDERRUN)
324    }
325    #[doc = "`1`"]
326    #[inline(always)]
327    pub fn underrun(self) -> &'a mut crate::W<REG> {
328        self.variant(RF_UDR_A::UNDERRUN)
329    }
330}
331#[doc = "Field `tf_ovf` reader - TXFIFO Overflow"]
332pub type TF_OVF_R = crate::BitReader<TF_OVF_A>;
333#[doc = "TXFIFO Overflow\n\nValue on reset: 0"]
334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
335pub enum TF_OVF_A {
336    #[doc = "0: `0`"]
337    NOT_OVERFLOW = 0,
338    #[doc = "1: `1`"]
339    OVERFLOW = 1,
340}
341impl From<TF_OVF_A> for bool {
342    #[inline(always)]
343    fn from(variant: TF_OVF_A) -> Self {
344        variant as u8 != 0
345    }
346}
347impl TF_OVF_R {
348    #[doc = "Get enumerated values variant"]
349    #[inline(always)]
350    pub const fn variant(&self) -> TF_OVF_A {
351        match self.bits {
352            false => TF_OVF_A::NOT_OVERFLOW,
353            true => TF_OVF_A::OVERFLOW,
354        }
355    }
356    #[doc = "`0`"]
357    #[inline(always)]
358    pub fn is_not_overflow(&self) -> bool {
359        *self == TF_OVF_A::NOT_OVERFLOW
360    }
361    #[doc = "`1`"]
362    #[inline(always)]
363    pub fn is_overflow(&self) -> bool {
364        *self == TF_OVF_A::OVERFLOW
365    }
366}
367#[doc = "Field `tf_ovf` writer - TXFIFO Overflow"]
368pub type TF_OVF_W<'a, REG> = crate::BitWriter<'a, REG, TF_OVF_A>;
369impl<'a, REG> TF_OVF_W<'a, REG>
370where
371    REG: crate::Writable + crate::RegisterSpec,
372{
373    #[doc = "`0`"]
374    #[inline(always)]
375    pub fn not_overflow(self) -> &'a mut crate::W<REG> {
376        self.variant(TF_OVF_A::NOT_OVERFLOW)
377    }
378    #[doc = "`1`"]
379    #[inline(always)]
380    pub fn overflow(self) -> &'a mut crate::W<REG> {
381        self.variant(TF_OVF_A::OVERFLOW)
382    }
383}
384#[doc = "Field `tf_udr` reader - TXFIFO Underrun"]
385pub type TF_UDR_R = crate::BitReader<TF_UDR_A>;
386#[doc = "TXFIFO Underrun\n\nValue on reset: 0"]
387#[derive(Clone, Copy, Debug, PartialEq, Eq)]
388pub enum TF_UDR_A {
389    #[doc = "0: `0`"]
390    NOT_UNDERRUN = 0,
391    #[doc = "1: `1`"]
392    UNDERRUN = 1,
393}
394impl From<TF_UDR_A> for bool {
395    #[inline(always)]
396    fn from(variant: TF_UDR_A) -> Self {
397        variant as u8 != 0
398    }
399}
400impl TF_UDR_R {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub const fn variant(&self) -> TF_UDR_A {
404        match self.bits {
405            false => TF_UDR_A::NOT_UNDERRUN,
406            true => TF_UDR_A::UNDERRUN,
407        }
408    }
409    #[doc = "`0`"]
410    #[inline(always)]
411    pub fn is_not_underrun(&self) -> bool {
412        *self == TF_UDR_A::NOT_UNDERRUN
413    }
414    #[doc = "`1`"]
415    #[inline(always)]
416    pub fn is_underrun(&self) -> bool {
417        *self == TF_UDR_A::UNDERRUN
418    }
419}
420#[doc = "Field `tf_udr` writer - TXFIFO Underrun"]
421pub type TF_UDR_W<'a, REG> = crate::BitWriter<'a, REG, TF_UDR_A>;
422impl<'a, REG> TF_UDR_W<'a, REG>
423where
424    REG: crate::Writable + crate::RegisterSpec,
425{
426    #[doc = "`0`"]
427    #[inline(always)]
428    pub fn not_underrun(self) -> &'a mut crate::W<REG> {
429        self.variant(TF_UDR_A::NOT_UNDERRUN)
430    }
431    #[doc = "`1`"]
432    #[inline(always)]
433    pub fn underrun(self) -> &'a mut crate::W<REG> {
434        self.variant(TF_UDR_A::UNDERRUN)
435    }
436}
437#[doc = "Field `tc` reader - Transfer Completed"]
438pub type TC_R = crate::BitReader<TC_A>;
439#[doc = "Transfer Completed\n\nValue on reset: 0"]
440#[derive(Clone, Copy, Debug, PartialEq, Eq)]
441pub enum TC_A {
442    #[doc = "0: `0`"]
443    BUSY = 0,
444    #[doc = "1: `1`"]
445    TRANSFER_COMPLETED = 1,
446}
447impl From<TC_A> for bool {
448    #[inline(always)]
449    fn from(variant: TC_A) -> Self {
450        variant as u8 != 0
451    }
452}
453impl TC_R {
454    #[doc = "Get enumerated values variant"]
455    #[inline(always)]
456    pub const fn variant(&self) -> TC_A {
457        match self.bits {
458            false => TC_A::BUSY,
459            true => TC_A::TRANSFER_COMPLETED,
460        }
461    }
462    #[doc = "`0`"]
463    #[inline(always)]
464    pub fn is_busy(&self) -> bool {
465        *self == TC_A::BUSY
466    }
467    #[doc = "`1`"]
468    #[inline(always)]
469    pub fn is_transfer_completed(&self) -> bool {
470        *self == TC_A::TRANSFER_COMPLETED
471    }
472}
473#[doc = "Field `tc` writer - Transfer Completed"]
474pub type TC_W<'a, REG> = crate::BitWriter<'a, REG, TC_A>;
475impl<'a, REG> TC_W<'a, REG>
476where
477    REG: crate::Writable + crate::RegisterSpec,
478{
479    #[doc = "`0`"]
480    #[inline(always)]
481    pub fn busy(self) -> &'a mut crate::W<REG> {
482        self.variant(TC_A::BUSY)
483    }
484    #[doc = "`1`"]
485    #[inline(always)]
486    pub fn transfer_completed(self) -> &'a mut crate::W<REG> {
487        self.variant(TC_A::TRANSFER_COMPLETED)
488    }
489}
490#[doc = "Field `ssi` reader - SS Invalid Enable"]
491pub type SSI_R = crate::BitReader;
492#[doc = "Field `ssi` writer - SS Invalid Enable"]
493pub type SSI_W<'a, REG> = crate::BitWriter<'a, REG>;
494impl R {
495    #[doc = "Bit 0 - RXFIFO Ready"]
496    #[inline(always)]
497    pub fn rf_rdy(&self) -> RF_RDY_R {
498        RF_RDY_R::new((self.bits & 1) != 0)
499    }
500    #[doc = "Bit 1 - RXFIFO Empty"]
501    #[inline(always)]
502    pub fn rf_emp(&self) -> RF_EMP_R {
503        RF_EMP_R::new(((self.bits >> 1) & 1) != 0)
504    }
505    #[doc = "Bit 2 - RXFIFO Full"]
506    #[inline(always)]
507    pub fn rf_full(&self) -> RF_FULL_R {
508        RF_FULL_R::new(((self.bits >> 2) & 1) != 0)
509    }
510    #[doc = "Bit 4 - TXFIFO Ready"]
511    #[inline(always)]
512    pub fn tf_ready(&self) -> TF_READY_R {
513        TF_READY_R::new(((self.bits >> 4) & 1) != 0)
514    }
515    #[doc = "Bit 5 - TXFIFO Empty"]
516    #[inline(always)]
517    pub fn tf_emp(&self) -> TF_EMP_R {
518        TF_EMP_R::new(((self.bits >> 5) & 1) != 0)
519    }
520    #[doc = "Bit 6 - TXFIFO Full"]
521    #[inline(always)]
522    pub fn tf_full(&self) -> TF_FULL_R {
523        TF_FULL_R::new(((self.bits >> 6) & 1) != 0)
524    }
525    #[doc = "Bit 8 - RXFIFO Overflow"]
526    #[inline(always)]
527    pub fn rf_ovf(&self) -> RF_OVF_R {
528        RF_OVF_R::new(((self.bits >> 8) & 1) != 0)
529    }
530    #[doc = "Bit 9 - RXFIFO Underrun"]
531    #[inline(always)]
532    pub fn rf_udr(&self) -> RF_UDR_R {
533        RF_UDR_R::new(((self.bits >> 9) & 1) != 0)
534    }
535    #[doc = "Bit 10 - TXFIFO Overflow"]
536    #[inline(always)]
537    pub fn tf_ovf(&self) -> TF_OVF_R {
538        TF_OVF_R::new(((self.bits >> 10) & 1) != 0)
539    }
540    #[doc = "Bit 11 - TXFIFO Underrun"]
541    #[inline(always)]
542    pub fn tf_udr(&self) -> TF_UDR_R {
543        TF_UDR_R::new(((self.bits >> 11) & 1) != 0)
544    }
545    #[doc = "Bit 12 - Transfer Completed"]
546    #[inline(always)]
547    pub fn tc(&self) -> TC_R {
548        TC_R::new(((self.bits >> 12) & 1) != 0)
549    }
550    #[doc = "Bit 13 - SS Invalid Enable"]
551    #[inline(always)]
552    pub fn ssi(&self) -> SSI_R {
553        SSI_R::new(((self.bits >> 13) & 1) != 0)
554    }
555}
556impl W {
557    #[doc = "Bit 0 - RXFIFO Ready"]
558    #[inline(always)]
559    #[must_use]
560    pub fn rf_rdy(&mut self) -> RF_RDY_W<SPI_ISR_SPEC> {
561        RF_RDY_W::new(self, 0)
562    }
563    #[doc = "Bit 1 - RXFIFO Empty"]
564    #[inline(always)]
565    #[must_use]
566    pub fn rf_emp(&mut self) -> RF_EMP_W<SPI_ISR_SPEC> {
567        RF_EMP_W::new(self, 1)
568    }
569    #[doc = "Bit 2 - RXFIFO Full"]
570    #[inline(always)]
571    #[must_use]
572    pub fn rf_full(&mut self) -> RF_FULL_W<SPI_ISR_SPEC> {
573        RF_FULL_W::new(self, 2)
574    }
575    #[doc = "Bit 4 - TXFIFO Ready"]
576    #[inline(always)]
577    #[must_use]
578    pub fn tf_ready(&mut self) -> TF_READY_W<SPI_ISR_SPEC> {
579        TF_READY_W::new(self, 4)
580    }
581    #[doc = "Bit 5 - TXFIFO Empty"]
582    #[inline(always)]
583    #[must_use]
584    pub fn tf_emp(&mut self) -> TF_EMP_W<SPI_ISR_SPEC> {
585        TF_EMP_W::new(self, 5)
586    }
587    #[doc = "Bit 6 - TXFIFO Full"]
588    #[inline(always)]
589    #[must_use]
590    pub fn tf_full(&mut self) -> TF_FULL_W<SPI_ISR_SPEC> {
591        TF_FULL_W::new(self, 6)
592    }
593    #[doc = "Bit 8 - RXFIFO Overflow"]
594    #[inline(always)]
595    #[must_use]
596    pub fn rf_ovf(&mut self) -> RF_OVF_W<SPI_ISR_SPEC> {
597        RF_OVF_W::new(self, 8)
598    }
599    #[doc = "Bit 9 - RXFIFO Underrun"]
600    #[inline(always)]
601    #[must_use]
602    pub fn rf_udr(&mut self) -> RF_UDR_W<SPI_ISR_SPEC> {
603        RF_UDR_W::new(self, 9)
604    }
605    #[doc = "Bit 10 - TXFIFO Overflow"]
606    #[inline(always)]
607    #[must_use]
608    pub fn tf_ovf(&mut self) -> TF_OVF_W<SPI_ISR_SPEC> {
609        TF_OVF_W::new(self, 10)
610    }
611    #[doc = "Bit 11 - TXFIFO Underrun"]
612    #[inline(always)]
613    #[must_use]
614    pub fn tf_udr(&mut self) -> TF_UDR_W<SPI_ISR_SPEC> {
615        TF_UDR_W::new(self, 11)
616    }
617    #[doc = "Bit 12 - Transfer Completed"]
618    #[inline(always)]
619    #[must_use]
620    pub fn tc(&mut self) -> TC_W<SPI_ISR_SPEC> {
621        TC_W::new(self, 12)
622    }
623    #[doc = "Bit 13 - SS Invalid Enable"]
624    #[inline(always)]
625    #[must_use]
626    pub fn ssi(&mut self) -> SSI_W<SPI_ISR_SPEC> {
627        SSI_W::new(self, 13)
628    }
629    #[doc = r" Writes raw bits to the register."]
630    #[doc = r""]
631    #[doc = r" # Safety"]
632    #[doc = r""]
633    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
634    #[inline(always)]
635    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
636        self.bits = bits;
637        self
638    }
639}
640#[doc = "SPI Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_isr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
641pub struct SPI_ISR_SPEC;
642impl crate::RegisterSpec for SPI_ISR_SPEC {
643    type Ux = u32;
644}
645#[doc = "`read()` method returns [`spi_isr::R`](R) reader structure"]
646impl crate::Readable for SPI_ISR_SPEC {}
647#[doc = "`write(|w| ..)` method takes [`spi_isr::W`](W) writer structure"]
648impl crate::Writable for SPI_ISR_SPEC {
649    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
650    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
651}
652#[doc = "`reset()` method sets spi_isr to value 0"]
653impl crate::Resettable for SPI_ISR_SPEC {
654    const RESET_VALUE: Self::Ux = 0;
655}
d1_pac/spi_dbi/spi_isr.rs

d1_pac/spi_dbi/
spi_isr.rs
