d1_pac/spi_dbi/
spi_gcr.rs

1#[doc = "Register `spi_gcr` reader"]
2pub type R = crate::R<SPI_GCR_SPEC>;
3#[doc = "Register `spi_gcr` writer"]
4pub type W = crate::W<SPI_GCR_SPEC>;
5#[doc = "Field `en` reader - SPI Module Enable Control"]
6pub type EN_R = crate::BitReader<EN_A>;
7#[doc = "SPI Module Enable Control\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum EN_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> EN_A {
25        match self.bits {
26            false => EN_A::DISABLE,
27            true => EN_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == EN_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == EN_A::ENABLE
39    }
40}
41#[doc = "Field `en` writer - SPI Module Enable Control"]
42pub type EN_W<'a, REG> = crate::BitWriter<'a, REG, EN_A>;
43impl<'a, REG> EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(EN_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(EN_A::ENABLE)
56    }
57}
58#[doc = "Field `mode` reader - SPI Function Mode Select"]
59pub type MODE_R = crate::BitReader<MODE_A>;
60#[doc = "SPI Function Mode Select\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum MODE_A {
63    #[doc = "0: `0`"]
64    SLAVE = 0,
65    #[doc = "1: `1`"]
66    MASTER = 1,
67}
68impl From<MODE_A> for bool {
69    #[inline(always)]
70    fn from(variant: MODE_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl MODE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> MODE_A {
78        match self.bits {
79            false => MODE_A::SLAVE,
80            true => MODE_A::MASTER,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_slave(&self) -> bool {
86        *self == MODE_A::SLAVE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_master(&self) -> bool {
91        *self == MODE_A::MASTER
92    }
93}
94#[doc = "Field `mode` writer - SPI Function Mode Select"]
95pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG, MODE_A>;
96impl<'a, REG> MODE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn slave(self) -> &'a mut crate::W<REG> {
103        self.variant(MODE_A::SLAVE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn master(self) -> &'a mut crate::W<REG> {
108        self.variant(MODE_A::MASTER)
109    }
110}
111#[doc = "Field `mode_selec` reader - Sample timing Mode Select"]
112pub type MODE_SELEC_R = crate::BitReader<MODE_SELEC_A>;
113#[doc = "Sample timing Mode Select\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum MODE_SELEC_A {
116    #[doc = "0: Old mode of Sample Timing"]
117    OLD_MODE = 0,
118    #[doc = "1: New mode of Sample Timing"]
119    NEW_MODE = 1,
120}
121impl From<MODE_SELEC_A> for bool {
122    #[inline(always)]
123    fn from(variant: MODE_SELEC_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl MODE_SELEC_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> MODE_SELEC_A {
131        match self.bits {
132            false => MODE_SELEC_A::OLD_MODE,
133            true => MODE_SELEC_A::NEW_MODE,
134        }
135    }
136    #[doc = "Old mode of Sample Timing"]
137    #[inline(always)]
138    pub fn is_old_mode(&self) -> bool {
139        *self == MODE_SELEC_A::OLD_MODE
140    }
141    #[doc = "New mode of Sample Timing"]
142    #[inline(always)]
143    pub fn is_new_mode(&self) -> bool {
144        *self == MODE_SELEC_A::NEW_MODE
145    }
146}
147#[doc = "Field `mode_selec` writer - Sample timing Mode Select"]
148pub type MODE_SELEC_W<'a, REG> = crate::BitWriter<'a, REG, MODE_SELEC_A>;
149impl<'a, REG> MODE_SELEC_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Old mode of Sample Timing"]
154    #[inline(always)]
155    pub fn old_mode(self) -> &'a mut crate::W<REG> {
156        self.variant(MODE_SELEC_A::OLD_MODE)
157    }
158    #[doc = "New mode of Sample Timing"]
159    #[inline(always)]
160    pub fn new_mode(self) -> &'a mut crate::W<REG> {
161        self.variant(MODE_SELEC_A::NEW_MODE)
162    }
163}
164#[doc = "Field `tp_en` reader - Transmit Pause Enable"]
165pub type TP_EN_R = crate::BitReader<TP_EN_A>;
166#[doc = "Transmit Pause Enable\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum TP_EN_A {
169    #[doc = "0: normal operation, ignore RXFIFO status"]
170    NORMAL = 0,
171    #[doc = "1: Stop transmit data when RXFIFO full"]
172    STOP_WHEN_FULL = 1,
173}
174impl From<TP_EN_A> for bool {
175    #[inline(always)]
176    fn from(variant: TP_EN_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl TP_EN_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> TP_EN_A {
184        match self.bits {
185            false => TP_EN_A::NORMAL,
186            true => TP_EN_A::STOP_WHEN_FULL,
187        }
188    }
189    #[doc = "normal operation, ignore RXFIFO status"]
190    #[inline(always)]
191    pub fn is_normal(&self) -> bool {
192        *self == TP_EN_A::NORMAL
193    }
194    #[doc = "Stop transmit data when RXFIFO full"]
195    #[inline(always)]
196    pub fn is_stop_when_full(&self) -> bool {
197        *self == TP_EN_A::STOP_WHEN_FULL
198    }
199}
200#[doc = "Field `tp_en` writer - Transmit Pause Enable"]
201pub type TP_EN_W<'a, REG> = crate::BitWriter<'a, REG, TP_EN_A>;
202impl<'a, REG> TP_EN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "normal operation, ignore RXFIFO status"]
207    #[inline(always)]
208    pub fn normal(self) -> &'a mut crate::W<REG> {
209        self.variant(TP_EN_A::NORMAL)
210    }
211    #[doc = "Stop transmit data when RXFIFO full"]
212    #[inline(always)]
213    pub fn stop_when_full(self) -> &'a mut crate::W<REG> {
214        self.variant(TP_EN_A::STOP_WHEN_FULL)
215    }
216}
217#[doc = "Field `srst` reader - Soft reset"]
218pub type SRST_R = crate::BitReader;
219#[doc = "Field `srst` writer - Soft reset"]
220pub type SRST_W<'a, REG> = crate::BitWriter<'a, REG>;
221impl R {
222    #[doc = "Bit 0 - SPI Module Enable Control"]
223    #[inline(always)]
224    pub fn en(&self) -> EN_R {
225        EN_R::new((self.bits & 1) != 0)
226    }
227    #[doc = "Bit 1 - SPI Function Mode Select"]
228    #[inline(always)]
229    pub fn mode(&self) -> MODE_R {
230        MODE_R::new(((self.bits >> 1) & 1) != 0)
231    }
232    #[doc = "Bit 2 - Sample timing Mode Select"]
233    #[inline(always)]
234    pub fn mode_selec(&self) -> MODE_SELEC_R {
235        MODE_SELEC_R::new(((self.bits >> 2) & 1) != 0)
236    }
237    #[doc = "Bit 7 - Transmit Pause Enable"]
238    #[inline(always)]
239    pub fn tp_en(&self) -> TP_EN_R {
240        TP_EN_R::new(((self.bits >> 7) & 1) != 0)
241    }
242    #[doc = "Bit 31 - Soft reset"]
243    #[inline(always)]
244    pub fn srst(&self) -> SRST_R {
245        SRST_R::new(((self.bits >> 31) & 1) != 0)
246    }
247}
248impl W {
249    #[doc = "Bit 0 - SPI Module Enable Control"]
250    #[inline(always)]
251    #[must_use]
252    pub fn en(&mut self) -> EN_W<SPI_GCR_SPEC> {
253        EN_W::new(self, 0)
254    }
255    #[doc = "Bit 1 - SPI Function Mode Select"]
256    #[inline(always)]
257    #[must_use]
258    pub fn mode(&mut self) -> MODE_W<SPI_GCR_SPEC> {
259        MODE_W::new(self, 1)
260    }
261    #[doc = "Bit 2 - Sample timing Mode Select"]
262    #[inline(always)]
263    #[must_use]
264    pub fn mode_selec(&mut self) -> MODE_SELEC_W<SPI_GCR_SPEC> {
265        MODE_SELEC_W::new(self, 2)
266    }
267    #[doc = "Bit 7 - Transmit Pause Enable"]
268    #[inline(always)]
269    #[must_use]
270    pub fn tp_en(&mut self) -> TP_EN_W<SPI_GCR_SPEC> {
271        TP_EN_W::new(self, 7)
272    }
273    #[doc = "Bit 31 - Soft reset"]
274    #[inline(always)]
275    #[must_use]
276    pub fn srst(&mut self) -> SRST_W<SPI_GCR_SPEC> {
277        SRST_W::new(self, 31)
278    }
279    #[doc = r" Writes raw bits to the register."]
280    #[doc = r""]
281    #[doc = r" # Safety"]
282    #[doc = r""]
283    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
284    #[inline(always)]
285    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
286        self.bits = bits;
287        self
288    }
289}
290#[doc = "SPI Global Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_gcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_gcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
291pub struct SPI_GCR_SPEC;
292impl crate::RegisterSpec for SPI_GCR_SPEC {
293    type Ux = u32;
294}
295#[doc = "`read()` method returns [`spi_gcr::R`](R) reader structure"]
296impl crate::Readable for SPI_GCR_SPEC {}
297#[doc = "`write(|w| ..)` method takes [`spi_gcr::W`](W) writer structure"]
298impl crate::Writable for SPI_GCR_SPEC {
299    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
300    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
301}
302#[doc = "`reset()` method sets spi_gcr to value 0"]
303impl crate::Resettable for SPI_GCR_SPEC {
304    const RESET_VALUE: Self::Ux = 0;
305}
d1_pac/spi_dbi/spi_gcr.rs

d1_pac/spi_dbi/
spi_gcr.rs
