d1_pac/spi_dbi/
spi_fcr.rs

1#[doc = "Register `spi_fcr` reader"]
2pub type R = crate::R<SPI_FCR_SPEC>;
3#[doc = "Register `spi_fcr` writer"]
4pub type W = crate::W<SPI_FCR_SPEC>;
5#[doc = "Field `rf_trig_level` reader - RXFIFO Ready Request Trigger Level"]
6pub type RF_TRIG_LEVEL_R = crate::FieldReader;
7#[doc = "Field `rf_trig_level` writer - RXFIFO Ready Request Trigger Level"]
8pub type RF_TRIG_LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `rf_drq_en` reader - RXFIFO DMA Request Enable"]
10pub type RF_DRQ_EN_R = crate::BitReader<RF_DRQ_EN_A>;
11#[doc = "RXFIFO DMA Request Enable\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum RF_DRQ_EN_A {
14    #[doc = "0: `0`"]
15    DISABLE = 0,
16    #[doc = "1: `1`"]
17    ENABLE = 1,
18}
19impl From<RF_DRQ_EN_A> for bool {
20    #[inline(always)]
21    fn from(variant: RF_DRQ_EN_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl RF_DRQ_EN_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> RF_DRQ_EN_A {
29        match self.bits {
30            false => RF_DRQ_EN_A::DISABLE,
31            true => RF_DRQ_EN_A::ENABLE,
32        }
33    }
34    #[doc = "`0`"]
35    #[inline(always)]
36    pub fn is_disable(&self) -> bool {
37        *self == RF_DRQ_EN_A::DISABLE
38    }
39    #[doc = "`1`"]
40    #[inline(always)]
41    pub fn is_enable(&self) -> bool {
42        *self == RF_DRQ_EN_A::ENABLE
43    }
44}
45#[doc = "Field `rf_drq_en` writer - RXFIFO DMA Request Enable"]
46pub type RF_DRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, RF_DRQ_EN_A>;
47impl<'a, REG> RF_DRQ_EN_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn disable(self) -> &'a mut crate::W<REG> {
54        self.variant(RF_DRQ_EN_A::DISABLE)
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn enable(self) -> &'a mut crate::W<REG> {
59        self.variant(RF_DRQ_EN_A::ENABLE)
60    }
61}
62#[doc = "Field `rf_test_en` reader - RXFIFO Test Mode Enable"]
63pub type RF_TEST_EN_R = crate::BitReader<RF_TEST_EN_A>;
64#[doc = "RXFIFO Test Mode Enable\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum RF_TEST_EN_A {
67    #[doc = "0: `0`"]
68    DISABLE = 0,
69    #[doc = "1: `1`"]
70    ENABLE = 1,
71}
72impl From<RF_TEST_EN_A> for bool {
73    #[inline(always)]
74    fn from(variant: RF_TEST_EN_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl RF_TEST_EN_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> RF_TEST_EN_A {
82        match self.bits {
83            false => RF_TEST_EN_A::DISABLE,
84            true => RF_TEST_EN_A::ENABLE,
85        }
86    }
87    #[doc = "`0`"]
88    #[inline(always)]
89    pub fn is_disable(&self) -> bool {
90        *self == RF_TEST_EN_A::DISABLE
91    }
92    #[doc = "`1`"]
93    #[inline(always)]
94    pub fn is_enable(&self) -> bool {
95        *self == RF_TEST_EN_A::ENABLE
96    }
97}
98#[doc = "Field `rf_test_en` writer - RXFIFO Test Mode Enable"]
99pub type RF_TEST_EN_W<'a, REG> = crate::BitWriter<'a, REG, RF_TEST_EN_A>;
100impl<'a, REG> RF_TEST_EN_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "`0`"]
105    #[inline(always)]
106    pub fn disable(self) -> &'a mut crate::W<REG> {
107        self.variant(RF_TEST_EN_A::DISABLE)
108    }
109    #[doc = "`1`"]
110    #[inline(always)]
111    pub fn enable(self) -> &'a mut crate::W<REG> {
112        self.variant(RF_TEST_EN_A::ENABLE)
113    }
114}
115#[doc = "Field `rf_rst` reader - RXFIFO Reset"]
116pub type RF_RST_R = crate::BitReader;
117#[doc = "Field `rf_rst` writer - RXFIFO Reset"]
118pub type RF_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
119#[doc = "Field `tf_trig_level` reader - TXFIFO Empty Request Trigger Level"]
120pub type TF_TRIG_LEVEL_R = crate::FieldReader;
121#[doc = "Field `tf_trig_level` writer - TXFIFO Empty Request Trigger Level"]
122pub type TF_TRIG_LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
123#[doc = "Field `tf_drq_en` reader - TXFIFO DMA Request Enable"]
124pub type TF_DRQ_EN_R = crate::BitReader<TF_DRQ_EN_A>;
125#[doc = "TXFIFO DMA Request Enable\n\nValue on reset: 0"]
126#[derive(Clone, Copy, Debug, PartialEq, Eq)]
127pub enum TF_DRQ_EN_A {
128    #[doc = "0: `0`"]
129    DISABLE = 0,
130    #[doc = "1: `1`"]
131    ENABLE = 1,
132}
133impl From<TF_DRQ_EN_A> for bool {
134    #[inline(always)]
135    fn from(variant: TF_DRQ_EN_A) -> Self {
136        variant as u8 != 0
137    }
138}
139impl TF_DRQ_EN_R {
140    #[doc = "Get enumerated values variant"]
141    #[inline(always)]
142    pub const fn variant(&self) -> TF_DRQ_EN_A {
143        match self.bits {
144            false => TF_DRQ_EN_A::DISABLE,
145            true => TF_DRQ_EN_A::ENABLE,
146        }
147    }
148    #[doc = "`0`"]
149    #[inline(always)]
150    pub fn is_disable(&self) -> bool {
151        *self == TF_DRQ_EN_A::DISABLE
152    }
153    #[doc = "`1`"]
154    #[inline(always)]
155    pub fn is_enable(&self) -> bool {
156        *self == TF_DRQ_EN_A::ENABLE
157    }
158}
159#[doc = "Field `tf_drq_en` writer - TXFIFO DMA Request Enable"]
160pub type TF_DRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, TF_DRQ_EN_A>;
161impl<'a, REG> TF_DRQ_EN_W<'a, REG>
162where
163    REG: crate::Writable + crate::RegisterSpec,
164{
165    #[doc = "`0`"]
166    #[inline(always)]
167    pub fn disable(self) -> &'a mut crate::W<REG> {
168        self.variant(TF_DRQ_EN_A::DISABLE)
169    }
170    #[doc = "`1`"]
171    #[inline(always)]
172    pub fn enable(self) -> &'a mut crate::W<REG> {
173        self.variant(TF_DRQ_EN_A::ENABLE)
174    }
175}
176#[doc = "Field `tf_test_en` reader - TXFIFO Test Mode Enable"]
177pub type TF_TEST_EN_R = crate::BitReader<TF_TEST_EN_A>;
178#[doc = "TXFIFO Test Mode Enable\n\nValue on reset: 0"]
179#[derive(Clone, Copy, Debug, PartialEq, Eq)]
180pub enum TF_TEST_EN_A {
181    #[doc = "0: `0`"]
182    DISABLE = 0,
183    #[doc = "1: `1`"]
184    ENABLE = 1,
185}
186impl From<TF_TEST_EN_A> for bool {
187    #[inline(always)]
188    fn from(variant: TF_TEST_EN_A) -> Self {
189        variant as u8 != 0
190    }
191}
192impl TF_TEST_EN_R {
193    #[doc = "Get enumerated values variant"]
194    #[inline(always)]
195    pub const fn variant(&self) -> TF_TEST_EN_A {
196        match self.bits {
197            false => TF_TEST_EN_A::DISABLE,
198            true => TF_TEST_EN_A::ENABLE,
199        }
200    }
201    #[doc = "`0`"]
202    #[inline(always)]
203    pub fn is_disable(&self) -> bool {
204        *self == TF_TEST_EN_A::DISABLE
205    }
206    #[doc = "`1`"]
207    #[inline(always)]
208    pub fn is_enable(&self) -> bool {
209        *self == TF_TEST_EN_A::ENABLE
210    }
211}
212#[doc = "Field `tf_test_en` writer - TXFIFO Test Mode Enable"]
213pub type TF_TEST_EN_W<'a, REG> = crate::BitWriter<'a, REG, TF_TEST_EN_A>;
214impl<'a, REG> TF_TEST_EN_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    #[doc = "`0`"]
219    #[inline(always)]
220    pub fn disable(self) -> &'a mut crate::W<REG> {
221        self.variant(TF_TEST_EN_A::DISABLE)
222    }
223    #[doc = "`1`"]
224    #[inline(always)]
225    pub fn enable(self) -> &'a mut crate::W<REG> {
226        self.variant(TF_TEST_EN_A::ENABLE)
227    }
228}
229#[doc = "Field `tf_rst` reader - TXFIFO Reset"]
230pub type TF_RST_R = crate::BitReader;
231#[doc = "Field `tf_rst` writer - TXFIFO Reset"]
232pub type TF_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
233impl R {
234    #[doc = "Bits 0:7 - RXFIFO Ready Request Trigger Level"]
235    #[inline(always)]
236    pub fn rf_trig_level(&self) -> RF_TRIG_LEVEL_R {
237        RF_TRIG_LEVEL_R::new((self.bits & 0xff) as u8)
238    }
239    #[doc = "Bit 8 - RXFIFO DMA Request Enable"]
240    #[inline(always)]
241    pub fn rf_drq_en(&self) -> RF_DRQ_EN_R {
242        RF_DRQ_EN_R::new(((self.bits >> 8) & 1) != 0)
243    }
244    #[doc = "Bit 14 - RXFIFO Test Mode Enable"]
245    #[inline(always)]
246    pub fn rf_test_en(&self) -> RF_TEST_EN_R {
247        RF_TEST_EN_R::new(((self.bits >> 14) & 1) != 0)
248    }
249    #[doc = "Bit 15 - RXFIFO Reset"]
250    #[inline(always)]
251    pub fn rf_rst(&self) -> RF_RST_R {
252        RF_RST_R::new(((self.bits >> 15) & 1) != 0)
253    }
254    #[doc = "Bits 16:23 - TXFIFO Empty Request Trigger Level"]
255    #[inline(always)]
256    pub fn tf_trig_level(&self) -> TF_TRIG_LEVEL_R {
257        TF_TRIG_LEVEL_R::new(((self.bits >> 16) & 0xff) as u8)
258    }
259    #[doc = "Bit 24 - TXFIFO DMA Request Enable"]
260    #[inline(always)]
261    pub fn tf_drq_en(&self) -> TF_DRQ_EN_R {
262        TF_DRQ_EN_R::new(((self.bits >> 24) & 1) != 0)
263    }
264    #[doc = "Bit 30 - TXFIFO Test Mode Enable"]
265    #[inline(always)]
266    pub fn tf_test_en(&self) -> TF_TEST_EN_R {
267        TF_TEST_EN_R::new(((self.bits >> 30) & 1) != 0)
268    }
269    #[doc = "Bit 31 - TXFIFO Reset"]
270    #[inline(always)]
271    pub fn tf_rst(&self) -> TF_RST_R {
272        TF_RST_R::new(((self.bits >> 31) & 1) != 0)
273    }
274}
275impl W {
276    #[doc = "Bits 0:7 - RXFIFO Ready Request Trigger Level"]
277    #[inline(always)]
278    #[must_use]
279    pub fn rf_trig_level(&mut self) -> RF_TRIG_LEVEL_W<SPI_FCR_SPEC> {
280        RF_TRIG_LEVEL_W::new(self, 0)
281    }
282    #[doc = "Bit 8 - RXFIFO DMA Request Enable"]
283    #[inline(always)]
284    #[must_use]
285    pub fn rf_drq_en(&mut self) -> RF_DRQ_EN_W<SPI_FCR_SPEC> {
286        RF_DRQ_EN_W::new(self, 8)
287    }
288    #[doc = "Bit 14 - RXFIFO Test Mode Enable"]
289    #[inline(always)]
290    #[must_use]
291    pub fn rf_test_en(&mut self) -> RF_TEST_EN_W<SPI_FCR_SPEC> {
292        RF_TEST_EN_W::new(self, 14)
293    }
294    #[doc = "Bit 15 - RXFIFO Reset"]
295    #[inline(always)]
296    #[must_use]
297    pub fn rf_rst(&mut self) -> RF_RST_W<SPI_FCR_SPEC> {
298        RF_RST_W::new(self, 15)
299    }
300    #[doc = "Bits 16:23 - TXFIFO Empty Request Trigger Level"]
301    #[inline(always)]
302    #[must_use]
303    pub fn tf_trig_level(&mut self) -> TF_TRIG_LEVEL_W<SPI_FCR_SPEC> {
304        TF_TRIG_LEVEL_W::new(self, 16)
305    }
306    #[doc = "Bit 24 - TXFIFO DMA Request Enable"]
307    #[inline(always)]
308    #[must_use]
309    pub fn tf_drq_en(&mut self) -> TF_DRQ_EN_W<SPI_FCR_SPEC> {
310        TF_DRQ_EN_W::new(self, 24)
311    }
312    #[doc = "Bit 30 - TXFIFO Test Mode Enable"]
313    #[inline(always)]
314    #[must_use]
315    pub fn tf_test_en(&mut self) -> TF_TEST_EN_W<SPI_FCR_SPEC> {
316        TF_TEST_EN_W::new(self, 30)
317    }
318    #[doc = "Bit 31 - TXFIFO Reset"]
319    #[inline(always)]
320    #[must_use]
321    pub fn tf_rst(&mut self) -> TF_RST_W<SPI_FCR_SPEC> {
322        TF_RST_W::new(self, 31)
323    }
324    #[doc = r" Writes raw bits to the register."]
325    #[doc = r""]
326    #[doc = r" # Safety"]
327    #[doc = r""]
328    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
329    #[inline(always)]
330    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
331        self.bits = bits;
332        self
333    }
334}
335#[doc = "SPI FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_fcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_fcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
336pub struct SPI_FCR_SPEC;
337impl crate::RegisterSpec for SPI_FCR_SPEC {
338    type Ux = u32;
339}
340#[doc = "`read()` method returns [`spi_fcr::R`](R) reader structure"]
341impl crate::Readable for SPI_FCR_SPEC {}
342#[doc = "`write(|w| ..)` method takes [`spi_fcr::W`](W) writer structure"]
343impl crate::Writable for SPI_FCR_SPEC {
344    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
345    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
346}
347#[doc = "`reset()` method sets spi_fcr to value 0"]
348impl crate::Resettable for SPI_FCR_SPEC {
349    const RESET_VALUE: Self::Ux = 0;
350}
d1_pac/spi_dbi/spi_fcr.rs

d1_pac/spi_dbi/
spi_fcr.rs
