d1_pac/spi_dbi/
dbi_int.rs

1#[doc = "Register `dbi_int` reader"]
2pub type R = crate::R<DBI_INT_SPEC>;
3#[doc = "Register `dbi_int` writer"]
4pub type W = crate::W<DBI_INT_SPEC>;
5#[doc = "Field `line_done_int_en` reader - "]
6pub type LINE_DONE_INT_EN_R = crate::BitReader;
7#[doc = "Field `line_done_int_en` writer - "]
8pub type LINE_DONE_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `fram_done_int_en` reader - "]
10pub type FRAM_DONE_INT_EN_R = crate::BitReader;
11#[doc = "Field `fram_done_int_en` writer - "]
12pub type FRAM_DONE_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `te_int_en` reader - "]
14pub type TE_INT_EN_R = crate::BitReader;
15#[doc = "Field `te_int_en` writer - "]
16pub type TE_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `rd_done_int_en` reader - "]
18pub type RD_DONE_INT_EN_R = crate::BitReader;
19#[doc = "Field `rd_done_int_en` writer - "]
20pub type RD_DONE_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `timer_int_en` reader - "]
22pub type TIMER_INT_EN_R = crate::BitReader;
23#[doc = "Field `timer_int_en` writer - "]
24pub type TIMER_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `dbi_fifo_full_int_en` reader - "]
26pub type DBI_FIFO_FULL_INT_EN_R = crate::BitReader;
27#[doc = "Field `dbi_fifo_full_int_en` writer - "]
28pub type DBI_FIFO_FULL_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `dbi_fifo_empty_int_en` reader - "]
30pub type DBI_FIFO_EMPTY_INT_EN_R = crate::BitReader;
31#[doc = "Field `dbi_fifo_empty_int_en` writer - "]
32pub type DBI_FIFO_EMPTY_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `line_done_int` reader - "]
34pub type LINE_DONE_INT_R = crate::BitReader;
35#[doc = "Field `line_done_int` writer - "]
36pub type LINE_DONE_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `fram_done_int` reader - "]
38pub type FRAM_DONE_INT_R = crate::BitReader;
39#[doc = "Field `fram_done_int` writer - "]
40pub type FRAM_DONE_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `te_int` reader - "]
42pub type TE_INT_R = crate::BitReader;
43#[doc = "Field `te_int` writer - "]
44pub type TE_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `rd_done_int` reader - "]
46pub type RD_DONE_INT_R = crate::BitReader;
47#[doc = "Field `rd_done_int` writer - "]
48pub type RD_DONE_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `timer_int` reader - "]
50pub type TIMER_INT_R = crate::BitReader;
51#[doc = "Field `timer_int` writer - "]
52pub type TIMER_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `dbi_fifo_full_int` reader - "]
54pub type DBI_FIFO_FULL_INT_R = crate::BitReader;
55#[doc = "Field `dbi_fifo_full_int` writer - "]
56pub type DBI_FIFO_FULL_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `dbi_fifo_empty_int` reader - "]
58pub type DBI_FIFO_EMPTY_INT_R = crate::BitReader;
59#[doc = "Field `dbi_fifo_empty_int` writer - "]
60pub type DBI_FIFO_EMPTY_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
61impl R {
62    #[doc = "Bit 0"]
63    #[inline(always)]
64    pub fn line_done_int_en(&self) -> LINE_DONE_INT_EN_R {
65        LINE_DONE_INT_EN_R::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bit 1"]
68    #[inline(always)]
69    pub fn fram_done_int_en(&self) -> FRAM_DONE_INT_EN_R {
70        FRAM_DONE_INT_EN_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    #[doc = "Bit 2"]
73    #[inline(always)]
74    pub fn te_int_en(&self) -> TE_INT_EN_R {
75        TE_INT_EN_R::new(((self.bits >> 2) & 1) != 0)
76    }
77    #[doc = "Bit 3"]
78    #[inline(always)]
79    pub fn rd_done_int_en(&self) -> RD_DONE_INT_EN_R {
80        RD_DONE_INT_EN_R::new(((self.bits >> 3) & 1) != 0)
81    }
82    #[doc = "Bit 4"]
83    #[inline(always)]
84    pub fn timer_int_en(&self) -> TIMER_INT_EN_R {
85        TIMER_INT_EN_R::new(((self.bits >> 4) & 1) != 0)
86    }
87    #[doc = "Bit 5"]
88    #[inline(always)]
89    pub fn dbi_fifo_full_int_en(&self) -> DBI_FIFO_FULL_INT_EN_R {
90        DBI_FIFO_FULL_INT_EN_R::new(((self.bits >> 5) & 1) != 0)
91    }
92    #[doc = "Bit 6"]
93    #[inline(always)]
94    pub fn dbi_fifo_empty_int_en(&self) -> DBI_FIFO_EMPTY_INT_EN_R {
95        DBI_FIFO_EMPTY_INT_EN_R::new(((self.bits >> 6) & 1) != 0)
96    }
97    #[doc = "Bit 8"]
98    #[inline(always)]
99    pub fn line_done_int(&self) -> LINE_DONE_INT_R {
100        LINE_DONE_INT_R::new(((self.bits >> 8) & 1) != 0)
101    }
102    #[doc = "Bit 9"]
103    #[inline(always)]
104    pub fn fram_done_int(&self) -> FRAM_DONE_INT_R {
105        FRAM_DONE_INT_R::new(((self.bits >> 9) & 1) != 0)
106    }
107    #[doc = "Bit 10"]
108    #[inline(always)]
109    pub fn te_int(&self) -> TE_INT_R {
110        TE_INT_R::new(((self.bits >> 10) & 1) != 0)
111    }
112    #[doc = "Bit 11"]
113    #[inline(always)]
114    pub fn rd_done_int(&self) -> RD_DONE_INT_R {
115        RD_DONE_INT_R::new(((self.bits >> 11) & 1) != 0)
116    }
117    #[doc = "Bit 12"]
118    #[inline(always)]
119    pub fn timer_int(&self) -> TIMER_INT_R {
120        TIMER_INT_R::new(((self.bits >> 12) & 1) != 0)
121    }
122    #[doc = "Bit 13"]
123    #[inline(always)]
124    pub fn dbi_fifo_full_int(&self) -> DBI_FIFO_FULL_INT_R {
125        DBI_FIFO_FULL_INT_R::new(((self.bits >> 13) & 1) != 0)
126    }
127    #[doc = "Bit 14"]
128    #[inline(always)]
129    pub fn dbi_fifo_empty_int(&self) -> DBI_FIFO_EMPTY_INT_R {
130        DBI_FIFO_EMPTY_INT_R::new(((self.bits >> 14) & 1) != 0)
131    }
132}
133impl W {
134    #[doc = "Bit 0"]
135    #[inline(always)]
136    #[must_use]
137    pub fn line_done_int_en(&mut self) -> LINE_DONE_INT_EN_W<DBI_INT_SPEC> {
138        LINE_DONE_INT_EN_W::new(self, 0)
139    }
140    #[doc = "Bit 1"]
141    #[inline(always)]
142    #[must_use]
143    pub fn fram_done_int_en(&mut self) -> FRAM_DONE_INT_EN_W<DBI_INT_SPEC> {
144        FRAM_DONE_INT_EN_W::new(self, 1)
145    }
146    #[doc = "Bit 2"]
147    #[inline(always)]
148    #[must_use]
149    pub fn te_int_en(&mut self) -> TE_INT_EN_W<DBI_INT_SPEC> {
150        TE_INT_EN_W::new(self, 2)
151    }
152    #[doc = "Bit 3"]
153    #[inline(always)]
154    #[must_use]
155    pub fn rd_done_int_en(&mut self) -> RD_DONE_INT_EN_W<DBI_INT_SPEC> {
156        RD_DONE_INT_EN_W::new(self, 3)
157    }
158    #[doc = "Bit 4"]
159    #[inline(always)]
160    #[must_use]
161    pub fn timer_int_en(&mut self) -> TIMER_INT_EN_W<DBI_INT_SPEC> {
162        TIMER_INT_EN_W::new(self, 4)
163    }
164    #[doc = "Bit 5"]
165    #[inline(always)]
166    #[must_use]
167    pub fn dbi_fifo_full_int_en(&mut self) -> DBI_FIFO_FULL_INT_EN_W<DBI_INT_SPEC> {
168        DBI_FIFO_FULL_INT_EN_W::new(self, 5)
169    }
170    #[doc = "Bit 6"]
171    #[inline(always)]
172    #[must_use]
173    pub fn dbi_fifo_empty_int_en(&mut self) -> DBI_FIFO_EMPTY_INT_EN_W<DBI_INT_SPEC> {
174        DBI_FIFO_EMPTY_INT_EN_W::new(self, 6)
175    }
176    #[doc = "Bit 8"]
177    #[inline(always)]
178    #[must_use]
179    pub fn line_done_int(&mut self) -> LINE_DONE_INT_W<DBI_INT_SPEC> {
180        LINE_DONE_INT_W::new(self, 8)
181    }
182    #[doc = "Bit 9"]
183    #[inline(always)]
184    #[must_use]
185    pub fn fram_done_int(&mut self) -> FRAM_DONE_INT_W<DBI_INT_SPEC> {
186        FRAM_DONE_INT_W::new(self, 9)
187    }
188    #[doc = "Bit 10"]
189    #[inline(always)]
190    #[must_use]
191    pub fn te_int(&mut self) -> TE_INT_W<DBI_INT_SPEC> {
192        TE_INT_W::new(self, 10)
193    }
194    #[doc = "Bit 11"]
195    #[inline(always)]
196    #[must_use]
197    pub fn rd_done_int(&mut self) -> RD_DONE_INT_W<DBI_INT_SPEC> {
198        RD_DONE_INT_W::new(self, 11)
199    }
200    #[doc = "Bit 12"]
201    #[inline(always)]
202    #[must_use]
203    pub fn timer_int(&mut self) -> TIMER_INT_W<DBI_INT_SPEC> {
204        TIMER_INT_W::new(self, 12)
205    }
206    #[doc = "Bit 13"]
207    #[inline(always)]
208    #[must_use]
209    pub fn dbi_fifo_full_int(&mut self) -> DBI_FIFO_FULL_INT_W<DBI_INT_SPEC> {
210        DBI_FIFO_FULL_INT_W::new(self, 13)
211    }
212    #[doc = "Bit 14"]
213    #[inline(always)]
214    #[must_use]
215    pub fn dbi_fifo_empty_int(&mut self) -> DBI_FIFO_EMPTY_INT_W<DBI_INT_SPEC> {
216        DBI_FIFO_EMPTY_INT_W::new(self, 14)
217    }
218    #[doc = r" Writes raw bits to the register."]
219    #[doc = r""]
220    #[doc = r" # Safety"]
221    #[doc = r""]
222    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
223    #[inline(always)]
224    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
225        self.bits = bits;
226        self
227    }
228}
229#[doc = "DBI Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_int::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_int::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
230pub struct DBI_INT_SPEC;
231impl crate::RegisterSpec for DBI_INT_SPEC {
232    type Ux = u32;
233}
234#[doc = "`read()` method returns [`dbi_int::R`](R) reader structure"]
235impl crate::Readable for DBI_INT_SPEC {}
236#[doc = "`write(|w| ..)` method takes [`dbi_int::W`](W) writer structure"]
237impl crate::Writable for DBI_INT_SPEC {
238    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
239    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
240}
241#[doc = "`reset()` method sets dbi_int to value 0"]
242impl crate::Resettable for DBI_INT_SPEC {
243    const RESET_VALUE: Self::Ux = 0;
244}
d1_pac/spi_dbi/dbi_int.rs

d1_pac/spi_dbi/
dbi_int.rs
