d1_pac/spi_dbi/
dbi_ctl_1.rs

1#[doc = "Register `dbi_ctl_1` reader"]
2pub type R = crate::R<DBI_CTL_1_SPEC>;
3#[doc = "Register `dbi_ctl_1` writer"]
4pub type W = crate::W<DBI_CTL_1_SPEC>;
5#[doc = "Field `rdbn` reader - Read Data Number of Bytes"]
6pub type RDBN_R = crate::FieldReader;
7#[doc = "Field `rdbn` writer - Read Data Number of Bytes"]
8pub type RDBN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `rcdc` reader - Read Command Dummy Cycles"]
10pub type RCDC_R = crate::FieldReader;
11#[doc = "Field `rcdc` writer - Read Command Dummy Cycles"]
12pub type RCDC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `rdat_lsb` reader - Bit Order of Read Data"]
14pub type RDAT_LSB_R = crate::BitReader;
15#[doc = "Field `rdat_lsb` writer - Bit Order of Read Data"]
16pub type RDAT_LSB_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `rgb16_data_source_select` reader - RGB 16 Data Source Select"]
18pub type RGB16_DATA_SOURCE_SELECT_R = crate::BitReader;
19#[doc = "Field `rgb16_data_source_select` writer - RGB 16 Data Source Select"]
20pub type RGB16_DATA_SOURCE_SELECT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `dcx_data` reader - DCX Data Value"]
22pub type DCX_DATA_R = crate::BitReader;
23#[doc = "Field `dcx_data` writer - DCX Data Value"]
24pub type DCX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `dbi_clko_inv` reader - DBI Clock Output Inverse"]
26pub type DBI_CLKO_INV_R = crate::BitReader;
27#[doc = "Field `dbi_clko_inv` writer - DBI Clock Output Inverse"]
28pub type DBI_CLKO_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `dbi_clko_mod` reader - DBI Output Clock Mode"]
30pub type DBI_CLKO_MOD_R = crate::BitReader<DBI_CLKO_MOD_A>;
31#[doc = "DBI Output Clock Mode\n\nValue on reset: 0"]
32#[derive(Clone, Copy, Debug, PartialEq, Eq)]
33pub enum DBI_CLKO_MOD_A {
34    #[doc = "0: `0`"]
35    ALWAYS_ON = 0,
36    #[doc = "1: `1`"]
37    AUTO_GATING = 1,
38}
39impl From<DBI_CLKO_MOD_A> for bool {
40    #[inline(always)]
41    fn from(variant: DBI_CLKO_MOD_A) -> Self {
42        variant as u8 != 0
43    }
44}
45impl DBI_CLKO_MOD_R {
46    #[doc = "Get enumerated values variant"]
47    #[inline(always)]
48    pub const fn variant(&self) -> DBI_CLKO_MOD_A {
49        match self.bits {
50            false => DBI_CLKO_MOD_A::ALWAYS_ON,
51            true => DBI_CLKO_MOD_A::AUTO_GATING,
52        }
53    }
54    #[doc = "`0`"]
55    #[inline(always)]
56    pub fn is_always_on(&self) -> bool {
57        *self == DBI_CLKO_MOD_A::ALWAYS_ON
58    }
59    #[doc = "`1`"]
60    #[inline(always)]
61    pub fn is_auto_gating(&self) -> bool {
62        *self == DBI_CLKO_MOD_A::AUTO_GATING
63    }
64}
65#[doc = "Field `dbi_clko_mod` writer - DBI Output Clock Mode"]
66pub type DBI_CLKO_MOD_W<'a, REG> = crate::BitWriter<'a, REG, DBI_CLKO_MOD_A>;
67impl<'a, REG> DBI_CLKO_MOD_W<'a, REG>
68where
69    REG: crate::Writable + crate::RegisterSpec,
70{
71    #[doc = "`0`"]
72    #[inline(always)]
73    pub fn always_on(self) -> &'a mut crate::W<REG> {
74        self.variant(DBI_CLKO_MOD_A::ALWAYS_ON)
75    }
76    #[doc = "`1`"]
77    #[inline(always)]
78    pub fn auto_gating(self) -> &'a mut crate::W<REG> {
79        self.variant(DBI_CLKO_MOD_A::AUTO_GATING)
80    }
81}
82#[doc = "Field `dbi_rxclk_inv` reader - DBI RX Clock Inverse"]
83pub type DBI_RXCLK_INV_R = crate::BitReader<DBI_RXCLK_INV_A>;
84#[doc = "DBI RX Clock Inverse\n\nValue on reset: 0"]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum DBI_RXCLK_INV_A {
87    #[doc = "0: `0`"]
88    POSITIVE = 0,
89    #[doc = "1: `1`"]
90    NEGATIVE = 1,
91}
92impl From<DBI_RXCLK_INV_A> for bool {
93    #[inline(always)]
94    fn from(variant: DBI_RXCLK_INV_A) -> Self {
95        variant as u8 != 0
96    }
97}
98impl DBI_RXCLK_INV_R {
99    #[doc = "Get enumerated values variant"]
100    #[inline(always)]
101    pub const fn variant(&self) -> DBI_RXCLK_INV_A {
102        match self.bits {
103            false => DBI_RXCLK_INV_A::POSITIVE,
104            true => DBI_RXCLK_INV_A::NEGATIVE,
105        }
106    }
107    #[doc = "`0`"]
108    #[inline(always)]
109    pub fn is_positive(&self) -> bool {
110        *self == DBI_RXCLK_INV_A::POSITIVE
111    }
112    #[doc = "`1`"]
113    #[inline(always)]
114    pub fn is_negative(&self) -> bool {
115        *self == DBI_RXCLK_INV_A::NEGATIVE
116    }
117}
118#[doc = "Field `dbi_rxclk_inv` writer - DBI RX Clock Inverse"]
119pub type DBI_RXCLK_INV_W<'a, REG> = crate::BitWriter<'a, REG, DBI_RXCLK_INV_A>;
120impl<'a, REG> DBI_RXCLK_INV_W<'a, REG>
121where
122    REG: crate::Writable + crate::RegisterSpec,
123{
124    #[doc = "`0`"]
125    #[inline(always)]
126    pub fn positive(self) -> &'a mut crate::W<REG> {
127        self.variant(DBI_RXCLK_INV_A::POSITIVE)
128    }
129    #[doc = "`1`"]
130    #[inline(always)]
131    pub fn negative(self) -> &'a mut crate::W<REG> {
132        self.variant(DBI_RXCLK_INV_A::NEGATIVE)
133    }
134}
135#[doc = "Field `rgb666_fmt` reader - 2 Data Lane RGB666 Format"]
136pub type RGB666_FMT_R = crate::FieldReader<RGB666_FMT_A>;
137#[doc = "2 Data Lane RGB666 Format\n\nValue on reset: 0"]
138#[derive(Clone, Copy, Debug, PartialEq, Eq)]
139#[repr(u8)]
140pub enum RGB666_FMT_A {
141    #[doc = "0: `0`"]
142    NORMAL = 0,
143    #[doc = "1: `1`"]
144    SPECIAL_ILITEK = 1,
145    #[doc = "2: `10`"]
146    SPECIAL_NEW_VISION = 2,
147}
148impl From<RGB666_FMT_A> for u8 {
149    #[inline(always)]
150    fn from(variant: RGB666_FMT_A) -> Self {
151        variant as _
152    }
153}
154impl crate::FieldSpec for RGB666_FMT_A {
155    type Ux = u8;
156}
157impl RGB666_FMT_R {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub const fn variant(&self) -> Option<RGB666_FMT_A> {
161        match self.bits {
162            0 => Some(RGB666_FMT_A::NORMAL),
163            1 => Some(RGB666_FMT_A::SPECIAL_ILITEK),
164            2 => Some(RGB666_FMT_A::SPECIAL_NEW_VISION),
165            _ => None,
166        }
167    }
168    #[doc = "`0`"]
169    #[inline(always)]
170    pub fn is_normal(&self) -> bool {
171        *self == RGB666_FMT_A::NORMAL
172    }
173    #[doc = "`1`"]
174    #[inline(always)]
175    pub fn is_special_ilitek(&self) -> bool {
176        *self == RGB666_FMT_A::SPECIAL_ILITEK
177    }
178    #[doc = "`10`"]
179    #[inline(always)]
180    pub fn is_special_new_vision(&self) -> bool {
181        *self == RGB666_FMT_A::SPECIAL_NEW_VISION
182    }
183}
184#[doc = "Field `rgb666_fmt` writer - 2 Data Lane RGB666 Format"]
185pub type RGB666_FMT_W<'a, REG> = crate::FieldWriter<'a, REG, 2, RGB666_FMT_A>;
186impl<'a, REG> RGB666_FMT_W<'a, REG>
187where
188    REG: crate::Writable + crate::RegisterSpec,
189    REG::Ux: From<u8>,
190{
191    #[doc = "`0`"]
192    #[inline(always)]
193    pub fn normal(self) -> &'a mut crate::W<REG> {
194        self.variant(RGB666_FMT_A::NORMAL)
195    }
196    #[doc = "`1`"]
197    #[inline(always)]
198    pub fn special_ilitek(self) -> &'a mut crate::W<REG> {
199        self.variant(RGB666_FMT_A::SPECIAL_ILITEK)
200    }
201    #[doc = "`10`"]
202    #[inline(always)]
203    pub fn special_new_vision(self) -> &'a mut crate::W<REG> {
204        self.variant(RGB666_FMT_A::SPECIAL_NEW_VISION)
205    }
206}
207#[doc = "Field `dbi_en_mode_sel` reader - DBI Enable Mode Select"]
208pub type DBI_EN_MODE_SEL_R = crate::FieldReader<DBI_EN_MODE_SEL_A>;
209#[doc = "DBI Enable Mode Select\n\nValue on reset: 0"]
210#[derive(Clone, Copy, Debug, PartialEq, Eq)]
211#[repr(u8)]
212pub enum DBI_EN_MODE_SEL_A {
213    #[doc = "0: `0`"]
214    DBI = 0,
215    #[doc = "1: `1`"]
216    SOFTWARE = 1,
217    #[doc = "2: `10`"]
218    TIMER = 2,
219    #[doc = "3: `11`"]
220    TE = 3,
221}
222impl From<DBI_EN_MODE_SEL_A> for u8 {
223    #[inline(always)]
224    fn from(variant: DBI_EN_MODE_SEL_A) -> Self {
225        variant as _
226    }
227}
228impl crate::FieldSpec for DBI_EN_MODE_SEL_A {
229    type Ux = u8;
230}
231impl DBI_EN_MODE_SEL_R {
232    #[doc = "Get enumerated values variant"]
233    #[inline(always)]
234    pub const fn variant(&self) -> DBI_EN_MODE_SEL_A {
235        match self.bits {
236            0 => DBI_EN_MODE_SEL_A::DBI,
237            1 => DBI_EN_MODE_SEL_A::SOFTWARE,
238            2 => DBI_EN_MODE_SEL_A::TIMER,
239            3 => DBI_EN_MODE_SEL_A::TE,
240            _ => unreachable!(),
241        }
242    }
243    #[doc = "`0`"]
244    #[inline(always)]
245    pub fn is_dbi(&self) -> bool {
246        *self == DBI_EN_MODE_SEL_A::DBI
247    }
248    #[doc = "`1`"]
249    #[inline(always)]
250    pub fn is_software(&self) -> bool {
251        *self == DBI_EN_MODE_SEL_A::SOFTWARE
252    }
253    #[doc = "`10`"]
254    #[inline(always)]
255    pub fn is_timer(&self) -> bool {
256        *self == DBI_EN_MODE_SEL_A::TIMER
257    }
258    #[doc = "`11`"]
259    #[inline(always)]
260    pub fn is_te(&self) -> bool {
261        *self == DBI_EN_MODE_SEL_A::TE
262    }
263}
264#[doc = "Field `dbi_en_mode_sel` writer - DBI Enable Mode Select"]
265pub type DBI_EN_MODE_SEL_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DBI_EN_MODE_SEL_A>;
266impl<'a, REG> DBI_EN_MODE_SEL_W<'a, REG>
267where
268    REG: crate::Writable + crate::RegisterSpec,
269    REG::Ux: From<u8>,
270{
271    #[doc = "`0`"]
272    #[inline(always)]
273    pub fn dbi(self) -> &'a mut crate::W<REG> {
274        self.variant(DBI_EN_MODE_SEL_A::DBI)
275    }
276    #[doc = "`1`"]
277    #[inline(always)]
278    pub fn software(self) -> &'a mut crate::W<REG> {
279        self.variant(DBI_EN_MODE_SEL_A::SOFTWARE)
280    }
281    #[doc = "`10`"]
282    #[inline(always)]
283    pub fn timer(self) -> &'a mut crate::W<REG> {
284        self.variant(DBI_EN_MODE_SEL_A::TIMER)
285    }
286    #[doc = "`11`"]
287    #[inline(always)]
288    pub fn te(self) -> &'a mut crate::W<REG> {
289        self.variant(DBI_EN_MODE_SEL_A::TE)
290    }
291}
292#[doc = "Field `dbi_soft_trg` reader - DBI Soft Trigger"]
293pub type DBI_SOFT_TRG_R = crate::BitReader;
294#[doc = "Field `dbi_soft_trg` writer - DBI Soft Trigger"]
295pub type DBI_SOFT_TRG_W<'a, REG> = crate::BitWriter<'a, REG>;
296impl R {
297    #[doc = "Bits 0:7 - Read Data Number of Bytes"]
298    #[inline(always)]
299    pub fn rdbn(&self) -> RDBN_R {
300        RDBN_R::new((self.bits & 0xff) as u8)
301    }
302    #[doc = "Bits 8:15 - Read Command Dummy Cycles"]
303    #[inline(always)]
304    pub fn rcdc(&self) -> RCDC_R {
305        RCDC_R::new(((self.bits >> 8) & 0xff) as u8)
306    }
307    #[doc = "Bit 20 - Bit Order of Read Data"]
308    #[inline(always)]
309    pub fn rdat_lsb(&self) -> RDAT_LSB_R {
310        RDAT_LSB_R::new(((self.bits >> 20) & 1) != 0)
311    }
312    #[doc = "Bit 21 - RGB 16 Data Source Select"]
313    #[inline(always)]
314    pub fn rgb16_data_source_select(&self) -> RGB16_DATA_SOURCE_SELECT_R {
315        RGB16_DATA_SOURCE_SELECT_R::new(((self.bits >> 21) & 1) != 0)
316    }
317    #[doc = "Bit 22 - DCX Data Value"]
318    #[inline(always)]
319    pub fn dcx_data(&self) -> DCX_DATA_R {
320        DCX_DATA_R::new(((self.bits >> 22) & 1) != 0)
321    }
322    #[doc = "Bit 23 - DBI Clock Output Inverse"]
323    #[inline(always)]
324    pub fn dbi_clko_inv(&self) -> DBI_CLKO_INV_R {
325        DBI_CLKO_INV_R::new(((self.bits >> 23) & 1) != 0)
326    }
327    #[doc = "Bit 24 - DBI Output Clock Mode"]
328    #[inline(always)]
329    pub fn dbi_clko_mod(&self) -> DBI_CLKO_MOD_R {
330        DBI_CLKO_MOD_R::new(((self.bits >> 24) & 1) != 0)
331    }
332    #[doc = "Bit 25 - DBI RX Clock Inverse"]
333    #[inline(always)]
334    pub fn dbi_rxclk_inv(&self) -> DBI_RXCLK_INV_R {
335        DBI_RXCLK_INV_R::new(((self.bits >> 25) & 1) != 0)
336    }
337    #[doc = "Bits 26:27 - 2 Data Lane RGB666 Format"]
338    #[inline(always)]
339    pub fn rgb666_fmt(&self) -> RGB666_FMT_R {
340        RGB666_FMT_R::new(((self.bits >> 26) & 3) as u8)
341    }
342    #[doc = "Bits 29:30 - DBI Enable Mode Select"]
343    #[inline(always)]
344    pub fn dbi_en_mode_sel(&self) -> DBI_EN_MODE_SEL_R {
345        DBI_EN_MODE_SEL_R::new(((self.bits >> 29) & 3) as u8)
346    }
347    #[doc = "Bit 31 - DBI Soft Trigger"]
348    #[inline(always)]
349    pub fn dbi_soft_trg(&self) -> DBI_SOFT_TRG_R {
350        DBI_SOFT_TRG_R::new(((self.bits >> 31) & 1) != 0)
351    }
352}
353impl W {
354    #[doc = "Bits 0:7 - Read Data Number of Bytes"]
355    #[inline(always)]
356    #[must_use]
357    pub fn rdbn(&mut self) -> RDBN_W<DBI_CTL_1_SPEC> {
358        RDBN_W::new(self, 0)
359    }
360    #[doc = "Bits 8:15 - Read Command Dummy Cycles"]
361    #[inline(always)]
362    #[must_use]
363    pub fn rcdc(&mut self) -> RCDC_W<DBI_CTL_1_SPEC> {
364        RCDC_W::new(self, 8)
365    }
366    #[doc = "Bit 20 - Bit Order of Read Data"]
367    #[inline(always)]
368    #[must_use]
369    pub fn rdat_lsb(&mut self) -> RDAT_LSB_W<DBI_CTL_1_SPEC> {
370        RDAT_LSB_W::new(self, 20)
371    }
372    #[doc = "Bit 21 - RGB 16 Data Source Select"]
373    #[inline(always)]
374    #[must_use]
375    pub fn rgb16_data_source_select(&mut self) -> RGB16_DATA_SOURCE_SELECT_W<DBI_CTL_1_SPEC> {
376        RGB16_DATA_SOURCE_SELECT_W::new(self, 21)
377    }
378    #[doc = "Bit 22 - DCX Data Value"]
379    #[inline(always)]
380    #[must_use]
381    pub fn dcx_data(&mut self) -> DCX_DATA_W<DBI_CTL_1_SPEC> {
382        DCX_DATA_W::new(self, 22)
383    }
384    #[doc = "Bit 23 - DBI Clock Output Inverse"]
385    #[inline(always)]
386    #[must_use]
387    pub fn dbi_clko_inv(&mut self) -> DBI_CLKO_INV_W<DBI_CTL_1_SPEC> {
388        DBI_CLKO_INV_W::new(self, 23)
389    }
390    #[doc = "Bit 24 - DBI Output Clock Mode"]
391    #[inline(always)]
392    #[must_use]
393    pub fn dbi_clko_mod(&mut self) -> DBI_CLKO_MOD_W<DBI_CTL_1_SPEC> {
394        DBI_CLKO_MOD_W::new(self, 24)
395    }
396    #[doc = "Bit 25 - DBI RX Clock Inverse"]
397    #[inline(always)]
398    #[must_use]
399    pub fn dbi_rxclk_inv(&mut self) -> DBI_RXCLK_INV_W<DBI_CTL_1_SPEC> {
400        DBI_RXCLK_INV_W::new(self, 25)
401    }
402    #[doc = "Bits 26:27 - 2 Data Lane RGB666 Format"]
403    #[inline(always)]
404    #[must_use]
405    pub fn rgb666_fmt(&mut self) -> RGB666_FMT_W<DBI_CTL_1_SPEC> {
406        RGB666_FMT_W::new(self, 26)
407    }
408    #[doc = "Bits 29:30 - DBI Enable Mode Select"]
409    #[inline(always)]
410    #[must_use]
411    pub fn dbi_en_mode_sel(&mut self) -> DBI_EN_MODE_SEL_W<DBI_CTL_1_SPEC> {
412        DBI_EN_MODE_SEL_W::new(self, 29)
413    }
414    #[doc = "Bit 31 - DBI Soft Trigger"]
415    #[inline(always)]
416    #[must_use]
417    pub fn dbi_soft_trg(&mut self) -> DBI_SOFT_TRG_W<DBI_CTL_1_SPEC> {
418        DBI_SOFT_TRG_W::new(self, 31)
419    }
420    #[doc = r" Writes raw bits to the register."]
421    #[doc = r""]
422    #[doc = r" # Safety"]
423    #[doc = r""]
424    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
425    #[inline(always)]
426    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
427        self.bits = bits;
428        self
429    }
430}
431#[doc = "DBI Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_ctl_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_ctl_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
432pub struct DBI_CTL_1_SPEC;
433impl crate::RegisterSpec for DBI_CTL_1_SPEC {
434    type Ux = u32;
435}
436#[doc = "`read()` method returns [`dbi_ctl_1::R`](R) reader structure"]
437impl crate::Readable for DBI_CTL_1_SPEC {}
438#[doc = "`write(|w| ..)` method takes [`dbi_ctl_1::W`](W) writer structure"]
439impl crate::Writable for DBI_CTL_1_SPEC {
440    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
441    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
442}
443#[doc = "`reset()` method sets dbi_ctl_1 to value 0"]
444impl crate::Resettable for DBI_CTL_1_SPEC {
445    const RESET_VALUE: Self::Ux = 0;
446}
d1_pac/spi_dbi/dbi_ctl_1.rs

d1_pac/spi_dbi/
dbi_ctl_1.rs
