1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x04],
5 spi_gcr: SPI_GCR,
6 spi_tcr: SPI_TCR,
7 _reserved2: [u8; 0x04],
8 spi_ier: SPI_IER,
9 spi_isr: SPI_ISR,
10 spi_fcr: SPI_FCR,
11 spi_fsr: SPI_FSR,
12 spi_wcr: SPI_WCR,
13 _reserved7: [u8; 0x04],
14 spi_samp_dl: SPI_SAMP_DL,
15 _reserved8: [u8; 0x04],
16 spi_mbc: SPI_MBC,
17 spi_mtc: SPI_MTC,
18 spi_bcc: SPI_BCC,
19 _reserved11: [u8; 0x04],
20 spi_batc: SPI_BATC,
21 spi_ba_ccr: SPI_BA_CCR,
22 spi_tbr: SPI_TBR,
23 spi_rbr: SPI_RBR,
24 _reserved15: [u8; 0x38],
25 spi_ndma_mode_ctl: SPI_NDMA_MODE_CTL,
26 _reserved16: [u8; 0x74],
27 dbi_ctl_0: DBI_CTL_0,
28 dbi_ctl_1: DBI_CTL_1,
29 dbi_ctl_2: DBI_CTL_2,
30 dbi_timer: DBI_TIMER,
31 dbi_video_szie: DBI_VIDEO_SZIE,
32 _reserved21: [u8; 0x0c],
33 dbi_int: DBI_INT,
34 dbi_debug_0: DBI_DEBUG_0,
35 dbi_debug_1: DBI_DEBUG_1,
36 _reserved24: [u8; 0xd4],
37 spi_txd: SPI_TXD,
38 _reserved25: [u8; 0xfc],
39 spi_rxd: SPI_RXD,
40}
41impl RegisterBlock {
42 #[doc = "0x04 - SPI Global Control Register"]
43 #[inline(always)]
44 pub const fn spi_gcr(&self) -> &SPI_GCR {
45 &self.spi_gcr
46 }
47 #[doc = "0x08 - SPI Transfer Control Register"]
48 #[inline(always)]
49 pub const fn spi_tcr(&self) -> &SPI_TCR {
50 &self.spi_tcr
51 }
52 #[doc = "0x10 - SPI Interrupt Control Register"]
53 #[inline(always)]
54 pub const fn spi_ier(&self) -> &SPI_IER {
55 &self.spi_ier
56 }
57 #[doc = "0x14 - SPI Interrupt Status Register"]
58 #[inline(always)]
59 pub const fn spi_isr(&self) -> &SPI_ISR {
60 &self.spi_isr
61 }
62 #[doc = "0x18 - SPI FIFO Control Register"]
63 #[inline(always)]
64 pub const fn spi_fcr(&self) -> &SPI_FCR {
65 &self.spi_fcr
66 }
67 #[doc = "0x1c - SPI FIFO Status Register"]
68 #[inline(always)]
69 pub const fn spi_fsr(&self) -> &SPI_FSR {
70 &self.spi_fsr
71 }
72 #[doc = "0x20 - SPI Wait Clock Register"]
73 #[inline(always)]
74 pub const fn spi_wcr(&self) -> &SPI_WCR {
75 &self.spi_wcr
76 }
77 #[doc = "0x28 - SPI Sample Delay Control Register"]
78 #[inline(always)]
79 pub const fn spi_samp_dl(&self) -> &SPI_SAMP_DL {
80 &self.spi_samp_dl
81 }
82 #[doc = "0x30 - SPI Master Burst Counter Register"]
83 #[inline(always)]
84 pub const fn spi_mbc(&self) -> &SPI_MBC {
85 &self.spi_mbc
86 }
87 #[doc = "0x34 - SPI Master Transmit Counter Register"]
88 #[inline(always)]
89 pub const fn spi_mtc(&self) -> &SPI_MTC {
90 &self.spi_mtc
91 }
92 #[doc = "0x38 - SPI Master Burst Control Register"]
93 #[inline(always)]
94 pub const fn spi_bcc(&self) -> &SPI_BCC {
95 &self.spi_bcc
96 }
97 #[doc = "0x40 - SPI Bit-Aligned Transfer Configure Register"]
98 #[inline(always)]
99 pub const fn spi_batc(&self) -> &SPI_BATC {
100 &self.spi_batc
101 }
102 #[doc = "0x44 - SPI Bit-Aligned Clock Configuration Register"]
103 #[inline(always)]
104 pub const fn spi_ba_ccr(&self) -> &SPI_BA_CCR {
105 &self.spi_ba_ccr
106 }
107 #[doc = "0x48 - SPI TX Bit Register\n\nVTB \\[31:0\\]: The Value of the Transmit Bits"]
108 #[inline(always)]
109 pub const fn spi_tbr(&self) -> &SPI_TBR {
110 &self.spi_tbr
111 }
112 #[doc = "0x4c - SPI RX Bit Register\n\nVRB \\[31:0\\]: The Value of the Receive Bits"]
113 #[inline(always)]
114 pub const fn spi_rbr(&self) -> &SPI_RBR {
115 &self.spi_rbr
116 }
117 #[doc = "0x88 - SPI Normal DMA Mode Control Register"]
118 #[inline(always)]
119 pub const fn spi_ndma_mode_ctl(&self) -> &SPI_NDMA_MODE_CTL {
120 &self.spi_ndma_mode_ctl
121 }
122 #[doc = "0x100 - DBI Control Register 0"]
123 #[inline(always)]
124 pub const fn dbi_ctl_0(&self) -> &DBI_CTL_0 {
125 &self.dbi_ctl_0
126 }
127 #[doc = "0x104 - DBI Control Register 1"]
128 #[inline(always)]
129 pub const fn dbi_ctl_1(&self) -> &DBI_CTL_1 {
130 &self.dbi_ctl_1
131 }
132 #[doc = "0x108 - DBI Control Register 2"]
133 #[inline(always)]
134 pub const fn dbi_ctl_2(&self) -> &DBI_CTL_2 {
135 &self.dbi_ctl_2
136 }
137 #[doc = "0x10c - DBI Timer Control Register"]
138 #[inline(always)]
139 pub const fn dbi_timer(&self) -> &DBI_TIMER {
140 &self.dbi_timer
141 }
142 #[doc = "0x110 - DBI Video Size Configuration Register"]
143 #[inline(always)]
144 pub const fn dbi_video_szie(&self) -> &DBI_VIDEO_SZIE {
145 &self.dbi_video_szie
146 }
147 #[doc = "0x120 - DBI Interrupt Register"]
148 #[inline(always)]
149 pub const fn dbi_int(&self) -> &DBI_INT {
150 &self.dbi_int
151 }
152 #[doc = "0x124 - DBI BEBUG 0 Register"]
153 #[inline(always)]
154 pub const fn dbi_debug_0(&self) -> &DBI_DEBUG_0 {
155 &self.dbi_debug_0
156 }
157 #[doc = "0x128 - DBI BEBUG 1 Register"]
158 #[inline(always)]
159 pub const fn dbi_debug_1(&self) -> &DBI_DEBUG_1 {
160 &self.dbi_debug_1
161 }
162 #[doc = "0x200 - SPI TX Data Register\n\nTDATA \\[31:0\\]: Transmit Data"]
163 #[inline(always)]
164 pub const fn spi_txd(&self) -> &SPI_TXD {
165 &self.spi_txd
166 }
167 #[doc = "0x300 - SPI RX Data Register\n\nRDATA \\[31:0\\]: Receive Data"]
168 #[inline(always)]
169 pub const fn spi_rxd(&self) -> &SPI_RXD {
170 &self.spi_rxd
171 }
172}
173#[doc = "spi_gcr (rw) register accessor: SPI Global Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_gcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_gcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_gcr`] module"]
174pub type SPI_GCR = crate::Reg<spi_gcr::SPI_GCR_SPEC>;
175#[doc = "SPI Global Control Register"]
176pub mod spi_gcr;
177#[doc = "spi_tcr (rw) register accessor: SPI Transfer Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_tcr`] module"]
178pub type SPI_TCR = crate::Reg<spi_tcr::SPI_TCR_SPEC>;
179#[doc = "SPI Transfer Control Register"]
180pub mod spi_tcr;
181#[doc = "spi_ier (rw) register accessor: SPI Interrupt Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ier`] module"]
182pub type SPI_IER = crate::Reg<spi_ier::SPI_IER_SPEC>;
183#[doc = "SPI Interrupt Control Register"]
184pub mod spi_ier;
185#[doc = "spi_isr (rw) register accessor: SPI Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_isr`] module"]
186pub type SPI_ISR = crate::Reg<spi_isr::SPI_ISR_SPEC>;
187#[doc = "SPI Interrupt Status Register"]
188pub mod spi_isr;
189#[doc = "spi_fcr (rw) register accessor: SPI FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_fcr`] module"]
190pub type SPI_FCR = crate::Reg<spi_fcr::SPI_FCR_SPEC>;
191#[doc = "SPI FIFO Control Register"]
192pub mod spi_fcr;
193#[doc = "spi_fsr (r) register accessor: SPI FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_fsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_fsr`] module"]
194pub type SPI_FSR = crate::Reg<spi_fsr::SPI_FSR_SPEC>;
195#[doc = "SPI FIFO Status Register"]
196pub mod spi_fsr;
197#[doc = "spi_wcr (rw) register accessor: SPI Wait Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_wcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_wcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_wcr`] module"]
198pub type SPI_WCR = crate::Reg<spi_wcr::SPI_WCR_SPEC>;
199#[doc = "SPI Wait Clock Register"]
200pub mod spi_wcr;
201#[doc = "spi_samp_dl (rw) register accessor: SPI Sample Delay Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_samp_dl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_samp_dl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_samp_dl`] module"]
202pub type SPI_SAMP_DL = crate::Reg<spi_samp_dl::SPI_SAMP_DL_SPEC>;
203#[doc = "SPI Sample Delay Control Register"]
204pub mod spi_samp_dl;
205#[doc = "spi_mbc (rw) register accessor: SPI Master Burst Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mbc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mbc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mbc`] module"]
206pub type SPI_MBC = crate::Reg<spi_mbc::SPI_MBC_SPEC>;
207#[doc = "SPI Master Burst Counter Register"]
208pub mod spi_mbc;
209#[doc = "spi_mtc (rw) register accessor: SPI Master Transmit Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mtc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mtc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mtc`] module"]
210pub type SPI_MTC = crate::Reg<spi_mtc::SPI_MTC_SPEC>;
211#[doc = "SPI Master Transmit Counter Register"]
212pub mod spi_mtc;
213#[doc = "spi_bcc (rw) register accessor: SPI Master Burst Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_bcc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_bcc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_bcc`] module"]
214pub type SPI_BCC = crate::Reg<spi_bcc::SPI_BCC_SPEC>;
215#[doc = "SPI Master Burst Control Register"]
216pub mod spi_bcc;
217#[doc = "spi_batc (rw) register accessor: SPI Bit-Aligned Transfer Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_batc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_batc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_batc`] module"]
218pub type SPI_BATC = crate::Reg<spi_batc::SPI_BATC_SPEC>;
219#[doc = "SPI Bit-Aligned Transfer Configure Register"]
220pub mod spi_batc;
221#[doc = "spi_ba_ccr (rw) register accessor: SPI Bit-Aligned Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ba_ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ba_ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ba_ccr`] module"]
222pub type SPI_BA_CCR = crate::Reg<spi_ba_ccr::SPI_BA_CCR_SPEC>;
223#[doc = "SPI Bit-Aligned Clock Configuration Register"]
224pub mod spi_ba_ccr;
225#[doc = "spi_tbr (rw) register accessor: SPI TX Bit Register\n\nVTB \\[31:0\\]: The Value of the Transmit Bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_tbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_tbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_tbr`] module"]
226pub type SPI_TBR = crate::Reg<spi_tbr::SPI_TBR_SPEC>;
227#[doc = "SPI TX Bit Register\n\nVTB \\[31:0\\]: The Value of the Transmit Bits"]
228pub mod spi_tbr;
229#[doc = "spi_rbr (rw) register accessor: SPI RX Bit Register\n\nVRB \\[31:0\\]: The Value of the Receive Bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rbr`] module"]
230pub type SPI_RBR = crate::Reg<spi_rbr::SPI_RBR_SPEC>;
231#[doc = "SPI RX Bit Register\n\nVRB \\[31:0\\]: The Value of the Receive Bits"]
232pub mod spi_rbr;
233#[doc = "spi_ndma_mode_ctl (rw) register accessor: SPI Normal DMA Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ndma_mode_ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ndma_mode_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ndma_mode_ctl`] module"]
234pub type SPI_NDMA_MODE_CTL = crate::Reg<spi_ndma_mode_ctl::SPI_NDMA_MODE_CTL_SPEC>;
235#[doc = "SPI Normal DMA Mode Control Register"]
236pub mod spi_ndma_mode_ctl;
237#[doc = "dbi_ctl_0 (rw) register accessor: DBI Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_ctl_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_ctl_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_ctl_0`] module"]
238pub type DBI_CTL_0 = crate::Reg<dbi_ctl_0::DBI_CTL_0_SPEC>;
239#[doc = "DBI Control Register 0"]
240pub mod dbi_ctl_0;
241#[doc = "dbi_ctl_1 (rw) register accessor: DBI Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_ctl_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_ctl_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_ctl_1`] module"]
242pub type DBI_CTL_1 = crate::Reg<dbi_ctl_1::DBI_CTL_1_SPEC>;
243#[doc = "DBI Control Register 1"]
244pub mod dbi_ctl_1;
245#[doc = "dbi_ctl_2 (rw) register accessor: DBI Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_ctl_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_ctl_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_ctl_2`] module"]
246pub type DBI_CTL_2 = crate::Reg<dbi_ctl_2::DBI_CTL_2_SPEC>;
247#[doc = "DBI Control Register 2"]
248pub mod dbi_ctl_2;
249#[doc = "dbi_timer (rw) register accessor: DBI Timer Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_timer::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_timer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_timer`] module"]
250pub type DBI_TIMER = crate::Reg<dbi_timer::DBI_TIMER_SPEC>;
251#[doc = "DBI Timer Control Register"]
252pub mod dbi_timer;
253#[doc = "dbi_video_szie (rw) register accessor: DBI Video Size Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_video_szie::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_video_szie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_video_szie`] module"]
254pub type DBI_VIDEO_SZIE = crate::Reg<dbi_video_szie::DBI_VIDEO_SZIE_SPEC>;
255#[doc = "DBI Video Size Configuration Register"]
256pub mod dbi_video_szie;
257#[doc = "dbi_int (rw) register accessor: DBI Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_int::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_int::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_int`] module"]
258pub type DBI_INT = crate::Reg<dbi_int::DBI_INT_SPEC>;
259#[doc = "DBI Interrupt Register"]
260pub mod dbi_int;
261#[doc = "dbi_debug_0 (r) register accessor: DBI BEBUG 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_debug_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_debug_0`] module"]
262pub type DBI_DEBUG_0 = crate::Reg<dbi_debug_0::DBI_DEBUG_0_SPEC>;
263#[doc = "DBI BEBUG 0 Register"]
264pub mod dbi_debug_0;
265#[doc = "dbi_debug_1 (r) register accessor: DBI BEBUG 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_debug_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_debug_1`] module"]
266pub type DBI_DEBUG_1 = crate::Reg<dbi_debug_1::DBI_DEBUG_1_SPEC>;
267#[doc = "DBI BEBUG 1 Register"]
268pub mod dbi_debug_1;
269#[doc = "spi_txd (rw) register accessor: SPI TX Data Register\n\nTDATA \\[31:0\\]: Transmit Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_txd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_txd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_txd`] module"]
270pub type SPI_TXD = crate::Reg<spi_txd::SPI_TXD_SPEC>;
271#[doc = "SPI TX Data Register\n\nTDATA \\[31:0\\]: Transmit Data"]
272pub mod spi_txd;
273#[doc = "spi_rxd (rw) register accessor: SPI RX Data Register\n\nRDATA \\[31:0\\]: Receive Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_rxd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_rxd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rxd`] module"]
274pub type SPI_RXD = crate::Reg<spi_rxd::SPI_RXD_SPEC>;
275#[doc = "SPI RX Data Register\n\nRDATA \\[31:0\\]: Receive Data"]
276pub mod spi_rxd;