d1_pac/spi0/
spi_ndma_mode_ctl.rs

1#[doc = "Register `spi_ndma_mode_ctl` reader"]
2pub type R = crate::R<SPI_NDMA_MODE_CTL_SPEC>;
3#[doc = "Register `spi_ndma_mode_ctl` writer"]
4pub type W = crate::W<SPI_NDMA_MODE_CTL_SPEC>;
5#[doc = "Field `spi_dma_wait` reader - "]
6pub type SPI_DMA_WAIT_R = crate::FieldReader;
7#[doc = "Field `spi_dma_wait` writer - "]
8pub type SPI_DMA_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `spi_ack_m` reader - SPI NDMA Acknowledge Mode"]
10pub type SPI_ACK_M_R = crate::BitReader<SPI_ACK_M_A>;
11#[doc = "SPI NDMA Acknowledge Mode\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum SPI_ACK_M_A {
14    #[doc = "0: `0`"]
15    IGNORE = 0,
16    #[doc = "1: `1`"]
17    AFTER_DETECT = 1,
18}
19impl From<SPI_ACK_M_A> for bool {
20    #[inline(always)]
21    fn from(variant: SPI_ACK_M_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl SPI_ACK_M_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> SPI_ACK_M_A {
29        match self.bits {
30            false => SPI_ACK_M_A::IGNORE,
31            true => SPI_ACK_M_A::AFTER_DETECT,
32        }
33    }
34    #[doc = "`0`"]
35    #[inline(always)]
36    pub fn is_ignore(&self) -> bool {
37        *self == SPI_ACK_M_A::IGNORE
38    }
39    #[doc = "`1`"]
40    #[inline(always)]
41    pub fn is_after_detect(&self) -> bool {
42        *self == SPI_ACK_M_A::AFTER_DETECT
43    }
44}
45#[doc = "Field `spi_ack_m` writer - SPI NDMA Acknowledge Mode"]
46pub type SPI_ACK_M_W<'a, REG> = crate::BitWriter<'a, REG, SPI_ACK_M_A>;
47impl<'a, REG> SPI_ACK_M_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn ignore(self) -> &'a mut crate::W<REG> {
54        self.variant(SPI_ACK_M_A::IGNORE)
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn after_detect(self) -> &'a mut crate::W<REG> {
59        self.variant(SPI_ACK_M_A::AFTER_DETECT)
60    }
61}
62#[doc = "Field `spi_act_m` reader - SPI NDMA Active Mode"]
63pub type SPI_ACT_M_R = crate::FieldReader<SPI_ACT_M_A>;
64#[doc = "SPI NDMA Active Mode\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum SPI_ACT_M_A {
68    #[doc = "0: `0`"]
69    LOW = 0,
70    #[doc = "1: `1`"]
71    HIGH = 1,
72    #[doc = "2: `10`"]
73    DRQ_CONTROL = 2,
74    #[doc = "3: `11`"]
75    CONTROLLER_CONTROL = 3,
76}
77impl From<SPI_ACT_M_A> for u8 {
78    #[inline(always)]
79    fn from(variant: SPI_ACT_M_A) -> Self {
80        variant as _
81    }
82}
83impl crate::FieldSpec for SPI_ACT_M_A {
84    type Ux = u8;
85}
86impl SPI_ACT_M_R {
87    #[doc = "Get enumerated values variant"]
88    #[inline(always)]
89    pub const fn variant(&self) -> SPI_ACT_M_A {
90        match self.bits {
91            0 => SPI_ACT_M_A::LOW,
92            1 => SPI_ACT_M_A::HIGH,
93            2 => SPI_ACT_M_A::DRQ_CONTROL,
94            3 => SPI_ACT_M_A::CONTROLLER_CONTROL,
95            _ => unreachable!(),
96        }
97    }
98    #[doc = "`0`"]
99    #[inline(always)]
100    pub fn is_low(&self) -> bool {
101        *self == SPI_ACT_M_A::LOW
102    }
103    #[doc = "`1`"]
104    #[inline(always)]
105    pub fn is_high(&self) -> bool {
106        *self == SPI_ACT_M_A::HIGH
107    }
108    #[doc = "`10`"]
109    #[inline(always)]
110    pub fn is_drq_control(&self) -> bool {
111        *self == SPI_ACT_M_A::DRQ_CONTROL
112    }
113    #[doc = "`11`"]
114    #[inline(always)]
115    pub fn is_controller_control(&self) -> bool {
116        *self == SPI_ACT_M_A::CONTROLLER_CONTROL
117    }
118}
119#[doc = "Field `spi_act_m` writer - SPI NDMA Active Mode"]
120pub type SPI_ACT_M_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, SPI_ACT_M_A>;
121impl<'a, REG> SPI_ACT_M_W<'a, REG>
122where
123    REG: crate::Writable + crate::RegisterSpec,
124    REG::Ux: From<u8>,
125{
126    #[doc = "`0`"]
127    #[inline(always)]
128    pub fn low(self) -> &'a mut crate::W<REG> {
129        self.variant(SPI_ACT_M_A::LOW)
130    }
131    #[doc = "`1`"]
132    #[inline(always)]
133    pub fn high(self) -> &'a mut crate::W<REG> {
134        self.variant(SPI_ACT_M_A::HIGH)
135    }
136    #[doc = "`10`"]
137    #[inline(always)]
138    pub fn drq_control(self) -> &'a mut crate::W<REG> {
139        self.variant(SPI_ACT_M_A::DRQ_CONTROL)
140    }
141    #[doc = "`11`"]
142    #[inline(always)]
143    pub fn controller_control(self) -> &'a mut crate::W<REG> {
144        self.variant(SPI_ACT_M_A::CONTROLLER_CONTROL)
145    }
146}
147impl R {
148    #[doc = "Bits 0:4"]
149    #[inline(always)]
150    pub fn spi_dma_wait(&self) -> SPI_DMA_WAIT_R {
151        SPI_DMA_WAIT_R::new((self.bits & 0x1f) as u8)
152    }
153    #[doc = "Bit 5 - SPI NDMA Acknowledge Mode"]
154    #[inline(always)]
155    pub fn spi_ack_m(&self) -> SPI_ACK_M_R {
156        SPI_ACK_M_R::new(((self.bits >> 5) & 1) != 0)
157    }
158    #[doc = "Bits 6:7 - SPI NDMA Active Mode"]
159    #[inline(always)]
160    pub fn spi_act_m(&self) -> SPI_ACT_M_R {
161        SPI_ACT_M_R::new(((self.bits >> 6) & 3) as u8)
162    }
163}
164impl W {
165    #[doc = "Bits 0:4"]
166    #[inline(always)]
167    #[must_use]
168    pub fn spi_dma_wait(&mut self) -> SPI_DMA_WAIT_W<SPI_NDMA_MODE_CTL_SPEC> {
169        SPI_DMA_WAIT_W::new(self, 0)
170    }
171    #[doc = "Bit 5 - SPI NDMA Acknowledge Mode"]
172    #[inline(always)]
173    #[must_use]
174    pub fn spi_ack_m(&mut self) -> SPI_ACK_M_W<SPI_NDMA_MODE_CTL_SPEC> {
175        SPI_ACK_M_W::new(self, 5)
176    }
177    #[doc = "Bits 6:7 - SPI NDMA Active Mode"]
178    #[inline(always)]
179    #[must_use]
180    pub fn spi_act_m(&mut self) -> SPI_ACT_M_W<SPI_NDMA_MODE_CTL_SPEC> {
181        SPI_ACT_M_W::new(self, 6)
182    }
183    #[doc = r" Writes raw bits to the register."]
184    #[doc = r""]
185    #[doc = r" # Safety"]
186    #[doc = r""]
187    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
188    #[inline(always)]
189    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
190        self.bits = bits;
191        self
192    }
193}
194#[doc = "SPI Normal DMA Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ndma_mode_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ndma_mode_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
195pub struct SPI_NDMA_MODE_CTL_SPEC;
196impl crate::RegisterSpec for SPI_NDMA_MODE_CTL_SPEC {
197    type Ux = u32;
198}
199#[doc = "`read()` method returns [`spi_ndma_mode_ctl::R`](R) reader structure"]
200impl crate::Readable for SPI_NDMA_MODE_CTL_SPEC {}
201#[doc = "`write(|w| ..)` method takes [`spi_ndma_mode_ctl::W`](W) writer structure"]
202impl crate::Writable for SPI_NDMA_MODE_CTL_SPEC {
203    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
204    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
205}
206#[doc = "`reset()` method sets spi_ndma_mode_ctl to value 0"]
207impl crate::Resettable for SPI_NDMA_MODE_CTL_SPEC {
208    const RESET_VALUE: Self::Ux = 0;
209}
d1_pac/spi0/spi_ndma_mode_ctl.rs

d1_pac/spi0/
spi_ndma_mode_ctl.rs
